Multi-chip packages with stabilized die pads

1. A multi-chip semiconductor device package assembly comprising:

a leadframe including:

a first die pad; and

a second die pad;

a first semiconductor die coupled to the first die pad;

a second semiconductor die coupled to the second die pad; and

a blank having a first portion coupled to the first die pad and a second portion coupled to the second die pad, such that the blank forms a bridge between the first die pad and the second die pad.

2. The multi-chip semiconductor device package assembly of claim 1 , wherein the leadframe further includes a third die pad, the multi-chip semiconductor device package assembly further comprising:

a third semiconductor die coupled to the third die pad, the blank having a third portion coupled to the third die pad, such that the blank further forms:

a bridge between the third die pad and the first die pad; and

a bridge between the third die pad and the second die pad.

3. The multi-chip semiconductor device package assembly of claim 2 , wherein the leadframe further includes a fourth die pad, the multi-chip semiconductor device package assembly further comprising:

a fourth semiconductor die coupled to the fourth die pad, the blank having a fourth portion coupled to the fourth die pad, such that the blank further forms:

a bridge between the fourth die pad and the first die pad;

a bridge between the fourth die pad and the second die pad; and

a bridge between the fourth die pad and the third die pad.

4. The multi-chip semiconductor device package assembly of claim 1 , wherein the blank is a first blank,

the leadframe further including:

a third die pad;

a fourth die pad,

the multi-chip semiconductor device package assembly further comprising:

a third semiconductor die coupled to the third die pad;

a fourth semiconductor die coupled to the fourth die pad; and

a second blank having a first portion coupled to the third die pad and a second portion coupled to the fourth die pad, such that the second blank forms a bridge between the third die pad and the fourth die pad.

5. The multi-chip semiconductor device package assembly of claim 1 , wherein the leadframe further includes:

a first signal lead; and

a second signal lead,

the multi-chip semiconductor device package assembly further comprising:

a first wire bond electrically coupling the first semiconductor die with the first signal lead; and

a second wire bond electrically coupling the second semiconductor die with the second signal lead.

6. The multi-chip semiconductor device package assembly of claim 1 , wherein the blank comprises a non-conductive material.

7. The multi-chip semiconductor device package assembly of claim 1 , wherein the blank comprises a conductive material.

8. The multi-chip semiconductor device package assembly of claim 7 , wherein:

the first portion of the blank is coupled to the first die pad with a non-conductive adhesive; and

the second portion of the blank is coupled to the second die pad with the non-conductive adhesive.

9. The multi-chip semiconductor device package assembly of claim 7 , wherein the blank electrically couples the first die pad with the second die pad.

10. The multi-chip semiconductor device package assembly of claim 1 , wherein:

the first portion of the blank is coupled to the first die pad with a non-conductive adhesive; and

the second portion of the blank is coupled to the second die pad with a non-conductive adhesive.

11. The multi-chip semiconductor device package assembly of claim 1 , wherein the blank includes at least one of a semiconductor material, a metal, an epoxy, a plastic or a ceramic.

12. The multi-chip semiconductor device package assembly of claim 1 , wherein the blank includes a third semiconductor die, the third semiconductor die being one of an inactive semiconductor die and a dummy semiconductor die.

13. The multi-chip semiconductor device package assembly of claim 1 , wherein the blank includes a non-conductive coating disposed on the first portion of the blank and the second portion of the blank.

14. A multi-chip semiconductor device package assembly comprising:

a leadframe including:

a first die pad;

a second die pad;

a first signal lead;

a second signal lead;

a third signal lead; and

a fourth signal lead;

a first semiconductor die coupled to the first die pad, a first side of the first semiconductor die being electrically coupled with the first signal lead;

a second semiconductor die coupled to the second die pad, a first side of the second semiconductor die being electrically coupled with the second signal lead; and

a blank having a first portion coupled to the first die pad and a second portion coupled to the second die pad, such that the blank forms a bridge between the first die pad and the second die pad,

a first wire bond electrically coupling a second side of the first semiconductor die with the third signal lead, the second side of the first semiconductor die being opposite the first side of the first semiconductor die; and

a second wire bond electrically coupling a second side of the second semiconductor die with the fourth signal lead, the second side fo the second semiconductor die being opposite the first side of the second semiconductor die.

15. The multi-chip semiconductor device package assembly of claim 14 , wherein the blank comprises a non-conductive material.

16. The multi-chip semiconductor device package assembly of claim 14 , wherein the blank comprises a conductive material.

17. The multi-chip semiconductor device package assembly of claim 16 , wherein the blank electrically couples the first die pad with the second die pad.

18. A method comprising:

affixing a first semiconductor die to a first die pad included in a leadframe;

affixing a second semiconductor die to a second die pad included in the leadframe; and

affixing a blank to the first die pad and the second die pad, such that a first portion of the blank is coupled to the first die pad and a second portion of the blank is coupled to the second die pad, the blank forming a bridge between the first die pad and the second die pad.

19. The method of claim 18 , further comprising:

forming a first wire bond electrically coupling the first semiconductor die with a first signal lead of the leadframe; and

forming a second wire bond electrically coupling the second semiconductor die with a second signal lead of the leadframe.

20. The method of claim 18 , wherein affixing the blank to the first die pad and the second die pad includes affixing the blank to the first die pad and the second die pad with a non-conductive adhesive.