Vertical field effect transistors incorporating U-shaped semiconductor bodies and methods
Disclosed is a semiconductor structure that includes a vertical field effect transistor (VFET) with a U-shaped semiconductor body. The semiconductor structure can be a standard VFET or a feedback VFET. In either case, the VFET includes a lower source/drain region, a semiconductor body on the lower source/drain region, and an upper source/drain region on the top of the semiconductor body. Rather than having an elongated fin shape, the semiconductor body folds back on itself in the Z direction so as to be essentially U-shaped (as viewed from above). Using a U-shaped semiconductor body reduces the dimension of the VFET in the Z direction without reducing the end-to-end length of the semiconductor body. Thus, VFET cell height can be reduced without reducing device drive current or violating critical design rules. Also disclosed is a method of forming a semiconductor structure that includes such a VFET with a U-shaped semiconductor body.
1. A semiconductor structure comprising:
a substrate; and
a vertical field effect transistor comprising:
a lower source/drain region on the substrate;
a semiconductor body having three segments comprising:
parallel segments above and immediately adjacent to the lower source/drain region and oriented in a first direction across the lower source/drain region; and
a connecting segment above and immediately adjacent to the lower source/drain region and oriented in a second direction across the lower source/drain region, wherein the connecting segment extends laterally between and is in direct contact with adjacent ends of the parallel segments such that the semiconductor body is essentially U-shaped, wherein the three segments have essentially equal heights; and
a single upper source/drain region on the three segments of the semiconductor body.
2. The semiconductor structure of claim 1 ,
wherein the lower source/drain region and the upper source/drain region have a same type conductivity, and
wherein the vertical field effect transistor further comprises:
a gate structure positioned laterally adjacent to sidewalls of the three segments of the semiconductor body so as to define a single channel region within the three segments of the semiconductor body;
a lower spacer electrically isolating the gate structure from the lower source/drain region;
an upper spacer electrically isolating the gate structure from the upper source/drain region; and
a dielectric sidewall spacer positioned laterally immediately adjacent to the upper source/drain region and further above and immediately adjacent to the upper spacer, wherein the dielectric sidewall spacer, the upper spacer, and the gate structure have essentially aligned vertical surfaces.
3. The semiconductor structure of claim 2 ,
wherein the vertical field effect transistor further comprises a gate contact between the parallel segments and having opposing sides contacting adjacent vertical surfaces, respectively, of the gate structure,
wherein the gate contact is electrically isolated from the lower source/drain region by the lower spacer and is electrically isolated from the upper source/drain region by the dielectric sidewall spacer.
4. The semiconductor structure of claim 2 , wherein the vertical field effect transistor further comprises:
a gate extension in contact with the gate structure; and
a gate extension contact on the gate extension.
5. The semiconductor structure of claim 1 ,
wherein the lower source/drain region has a first-type conductivity,
wherein the upper source/drain region has a second-type conductivity that is different than the first-type conductivity, and
wherein the vertical field effect transistor further comprises:
a first gate structure laterally surrounding a lower portion of the three segments of the semiconductor body;
a second gate structure laterally surrounding an upper portion of the three segments of the semiconductor body;
a lower spacer electrically isolating the first gate structure from the lower source/drain region;
a middle spacer electrically isolating the first gate structure from the second gate structure; and
an upper spacer electrically isolating the second gate structure from the upper source/drain region.
6. The semiconductor structure of claim 5 , wherein the vertical field effect transistor further comprises:
a gate extension in contact with the first gate structure; and
a gate extension contact on the gate extension.
7. The semiconductor structure of claim 5 , wherein the vertical field effect transistor further comprises a gate contact between the parallel segments above a level of the middle spacer and contacting the second gate structure.
8. The semiconductor structure of claim 1 , further comprising multiple vertical field effect transistors in adjacent rows separated by a space,
wherein all semiconductor bodies of the vertical field effect transistors in a given row are essentially U-shaped and have open ends adjacent to the space, and
wherein the semiconductor bodies of each pair of vertical field effect transistors on opposite sides of the space have aligned parallel segments.
9. A semiconductor structure comprising:
a substrate; and
a vertical field effect transistor comprising:
a lower source/drain region on the substrate;
a semiconductor body comprising:
parallel segments above and immediately adjacent to the lower source/drain region; and
a connecting segment above and immediately adjacent to the lower source/drain region and extending laterally between adjacent ends of the parallel segments, wherein the parallel segments and the connecting segment have essentially equal heights; and
an upper source/drain region on the semiconductor body,
wherein the lower source/drain region and the upper source/drain region have a same type conductivity,
wherein the vertical field effect transistor further comprises:
a gate structure positioned laterally adjacent to sidewalls of the semiconductor body so as to define a channel region within the semiconductor body;
a lower spacer electrically isolating the gate structure from the lower source/drain region;
an upper spacer electrically isolating the gate structure from the upper source/drain region;
a dielectric sidewall spacer on the upper source/drain region above the upper spacer;
a gate extension in contact with the gate structure; and
a gate extension contact on the gate extension.
10. The semiconductor structure of claim 9 , wherein the gate extension and the gate structure comprise continuous portions of patterned gate material.
11. The semiconductor structure of claim 9 , wherein the vertical field effect transistor further comprises:
a metal plug above and immediately adjacent to the upper source/drain region; and
dielectric plug cap above and immediately adjacent to the metal plug, wherein the dielectric sidewall spacer is positioned laterally immediately adjacent to opposing sidewalls of the upper source/drain region, the metal plug and the dielectric plug cap.
12. The semiconductor structure of claim 11 , wherein the vertical field effect transistor further comprises an upper source/drain region contact that extends through interlayer dielectric material to the dielectric plug cap and further extends through the dielectric plug cap to the metal plug.
13. The semiconductor structure of claim 12 , wherein the upper source/drain contact has an upper portion within the interlayer dielectric material above and traversing the parallel segments of the semiconductor body and lower portions that extend through the dielectric plug cap to the metal plug above the parallel segments, respectively.
14. The semiconductor structure of claim 9 , further comprising multiple vertical field effect transistors in adjacent rows separated by a space,
wherein all semiconductor bodies of the vertical field effect transistors in a given row have open ends adjacent to the space, and
wherein the semiconductor bodies of each pair of vertical field effect transistors on opposite sides of the space have aligned parallel segments.
15. A semiconductor structure comprising:
a substrate; and
a vertical field effect transistor comprising:
a lower source/drain region on the substrate;
a semiconductor body comprising:
parallel segments above and immediately adjacent to the lower source/drain region; and
a connecting segment above and immediately adjacent to the lower source/drain region and extending laterally between adjacent ends of the parallel segments, wherein the parallel segments and the connecting segment have essentially equal heights; and
an upper source/drain region on the semiconductor body,
wherein the lower source/drain region has a first-type conductivity,
wherein the upper source/drain region has a second-type conductivity that is different than the first-type conductivity, and
wherein the vertical field effect transistor further comprises:
a first gate structure laterally surrounding a lower portion of the semiconductor body;
a second gate structure laterally surrounding an upper portion of the semiconductor body;
a lower spacer electrically isolating the first gate structure from the lower source/drain region;
a middle spacer electrically isolating the first gate structure from the second gate structure; and
an upper spacer electrically isolating the second gate structure from the upper source/drain region.
16. The semiconductor structure of claim 15 , wherein the vertical field effect transistor further comprises:
a gate extension in contact with the first gate structure; and
a gate extension contact on the gate extension.
17. The semiconductor structure of claim 15 , wherein the vertical field effect transistor further comprises a gate contact between the parallel segments above a level of the middle spacer and contacting the second gate structure.
18. The semiconductor structure of claim 15 , wherein the vertical field effect transistor further comprises:
a metal plug above and immediately adjacent to the upper source/drain region;
dielectric plug cap above and immediately adjacent to the metal plug;
a dielectric sidewall spacer above the upper spacer and positioned laterally immediately adjacent to opposing sidewalls of the upper source/drain region, the metal plug and the dielectric plug cap; and
an upper source/drain region contact that extends through interlayer dielectric material and the dielectric plug cap to the metal plug.
19. The semiconductor structure of claim 18 , wherein the upper source/drain contact has an upper portion within the interlayer dielectric material above and traversing the parallel segments of the semiconductor body and lower portions that extend through the dielectric plug cap to the metal plug above the parallel segments, respectively, and wherein the lower portions are physically separated by the interlayer dielectric material.
20. The semiconductor structure of claim 15 , further comprising multiple vertical field effect transistors in adjacent rows separated by a space,
wherein all semiconductor bodies of the vertical field effect transistors in a given row have open ends adjacent to the space, and
wherein the semiconductor bodies of each pair of vertical field effect transistors on opposite sides of the space have aligned parallel segments.