IP Library Granted Patent US 12,457,762
Granted Patent B2
US 12,457,762 · App. 17/644,528 · Granted Oct 28, 2025

Cross bar vertical FETs

Inventors: Brent A. Anderson (Jericho, VT); Junli Wang (Slingerlands, NY); Indira Seshadri (Niskayuna, NY); Ruilong Xie (Niskayuna, NY); Dechao Guo (Niskayuna, NY)
Assignee: International Business Machines Corporation
H10D30/0243H10D30/6212H10D64/015
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Quick Facts
Patent No.
US 12,457,762
App. No.
17/644,528
Granted
Oct 28, 2025
Kind
B2
Abstract

The embodiments herein describe a crossbar VFET where the crossbar channel (or fin) that extends between a pair of channels (fins) has reduced corner rounding, or no corner rounding. This can be achieved by developing a masking feature before etching the channels in the VFET that results in reduced, or no corner rounding in the channel structure etched using the masking feature.

Claims (22)

1 . A vertical field effect transistor (VFET), comprising:

a first vertical channel;

a second vertical channel, wherein the first and second vertical channels extend in a first direction;

a horizontal channel disposed between the first and second vertical channels and extending in a second direction substantially perpendicular to the first direction, wherein the horizontal channel comprises:

a first end, wherein the first end and the first vertical channel are separated by a first gap; and

a second end opposite the first end, wherein the second end and the second vertical channel are separated by a second gap that is different than the first gap, and wherein the first end is closer to the first vertical channel than the second end; and

a source region and a drain region coupled to the first and second vertical channels.

2 . The VFET of claim 1 , wherein the first and second gaps are between the first and second ends of the horizontal channel and respective sides of the first and second vertical channels.

3 . The VFET of claim 1 , wherein the first and second gaps are between upper portions and lower portions of the first and second vertical channels, wherein the horizontal channel is aligned with the first and second gaps.

4 . The VFET of claim 1 , wherein the first and second vertical channels and the horizontal channel form an H-shape in a top down view.

5 . The VFET of claim 1 , wherein the first and second vertical channels and the horizontal channel comprise a semiconductor material.

6 . A vertical field effect transistor (VFET), comprising:

a first vertical channel;

a second vertical channel, wherein the first and second vertical channels extend in a first direction;

a horizontal channel disposed between the first and second the vertical channels and extending in a second direction substantially perpendicular to the first direction, wherein the horizontal channel comprises:

a first end;

a second end opposite the first end; and

a middle portion centered relative to the first and second ends, wherein the first end contacts the first vertical channel, where the second end contacts the second vertical channel, and wherein the first and second ends have a reduced width relative to a width of the middle portion; and

a source region and a drain region coupled to the first and second vertical channels.

7 . The VFET of claim 6 , wherein the first and second vertical channels and the horizontal channel form an H-shape in a top down view.

8 . The VFET of claim 6 , wherein the horizontal channel comprises notches at the first and second ends.

9 . The VFET of claim 6 , wherein the first and second vertical channels and the horizontal channel are fins of the VFET.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 15, 2021
From: ANDERSON, BRENT A.; WANG, JUNLI; SESHADRI, INDIRA; XIE, RUILONG; GUO, DECHAO
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 058402/0023 →
Continuity (1)
Related Publication 20230187541A1 · Jun 15, 2023
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