H-shaped VFET with increased current drivability

1. A method of forming a fin structure for a vertical field effect transistor (VFET), the method comprising the steps of:

depositing a hardmask onto a substrate;

depositing a mandrel material onto the hardmask;

patterning the mandrel material along a first direction to form first mandrels;

forming first spacers alongside the first mandrels;

filling gaps between the first mandrels with additional mandrel material to form second mandrels in between the first mandrels;

patterning the first mandrels, the first spacers and the second mandrels along a second direction, wherein the second direction is perpendicular to the first direction;

forming second spacers, perpendicular to the first spacers, alongside the first mandrels and the second mandrels;

selectively removing the first mandrels and the second mandrels leaving behind a ladder-shaped pattern formed by the first spacers and the second spacers;

transferring the ladder-shaped pattern to the hardmask; and

transferring the ladder-shaped pattern from the hardmask to the substrate to form a first fin adjacent to a second fin, and at least one cross fin interconnecting the first fin and the second fin; and

cutting the ladder-shaped pattern in the substrate into individual fin structures, wherein cuts made during the cutting are located to form each individual fin structure comprising: a first cross fin interconnecting the first fin and the second fin at one end of the individual fin structure, and a second cross fin interconnecting the first fin and the second fin at another end of the individual fin structure in an O-shaped fin structure.

2. The method of claim 1 , wherein the first mandrels and the second mandrels both comprise a material selected from the group consisting of: amorphous silicon, amorphous carbon, and combinations thereof.

3. The method of claim 1 , wherein the first spacers and the second spacers both comprise silicon dioxide.

4. The method of claim 1 , wherein the at least one cross fin is oriented orthogonal to the first fin and the second fin and interconnects the first fin and the second fin at a center of the first fin and the second fin in an H-shaped fin structure.

5. The method of claim 1 , wherein the ladder-shaped pattern in the substrate comprises multiple cross fins interconnecting the first fin and the second fin.

6. A method of forming a VFET device, the method comprising the steps of:

forming a fin structure in a substrate, the fin structure comprising a first fin adjacent to a second fin, and at least one cross fin interconnecting the first fin and the second fin;

forming bottom source and drains in the substrate beneath the fin structure;

forming bottom spacers on the bottom source and drains;

forming a gate around the fin structure over the bottom spacers;

forming top spacers above the gate; and

forming top source and drains at a top of the fin structure.

7. The method of claim 6 , wherein the step of forming the fin structure comprises the steps of:

depositing a hardmask onto a substrate;

depositing a mandrel material onto the hardmask;

patterning the mandrel material along a first direction to form first mandrels;

forming first spacers alongside the first mandrels;

filling gaps between the first mandrels with additional mandrel material to form second mandrels in between the first mandrels;

patterning the first mandrels, the first spacers and the second mandrels along a second direction, wherein the second direction is perpendicular to the first direction;

forming second spacers, perpendicular to the first spacers, alongside the first mandrels and the second mandrels;

selectively removing the first mandrels and the second mandrels leaving behind a ladder-shaped pattern formed by the first spacers and the second spacers;

transferring the ladder-shaped pattern to the hardmask; and

transferring the ladder-shaped pattern from the hardmask to the substrate to form the fin structure.

8. The method of claim 7 , wherein the first mandrels and the second mandrels both comprise a material selected from the group consisting of: amorphous silicon, amorphous carbon, and combinations thereof.

9. The method of claim 7 , wherein the first spacers and the second spacers both comprise silicon dioxide.

10. The method of claim 6 , wherein the at least one cross fin is oriented orthogonal to the first fin and the second fin and interconnects the first fin and the second fin at a center of the first fin and the second fin in an H-shaped fin structure.

11. The method of claim 6 , wherein the fin structure comprises multiple cross fins.

12. The method of claim 11 , wherein a first cross fin interconnects the first fin and the second fin at one end of the first fin and the second fin, and wherein a second cross fin interconnects the first fin and the second fin at another end of the first fin and the second fin in an O-shaped fin structure.

13. The method of claim 6 , wherein the step of forming the gate comprises:

depositing a gate dielectric around the fin structure; and

depositing a gate conductor on the gate dielectric.

14. The method of claim 13 , wherein the gate dielectric comprises a high-κ gate dielectric selected from the group consisting of: hafnium oxide, lanthanum oxide, and combinations thereof.

15. The method of claim 13 , wherein the gate conductor comprises a workfunction-setting metal selected from the group consisting of: titanium nitride, tantalum nitride, aluminum-containing alloys, titanium aluminide, titanium aluminum nitride, titanium aluminum carbide, tantalum aluminide, tantalum aluminum nitride, tantalum aluminum carbide, tungsten, and combinations thereof.

16. A VFET fin structure, comprising:

a first fin adjacent to a second fin; and

at least one cross fin interconnecting the first fin and the second fin, wherein the at least one cross fin is oriented at an angle θ<90° relative to the first fin and the second fin, and wherein the at least one cross fin interconnects the first fin and the second fin in an N-shaped fin structure.

17. The VFET fin structure of claim 16 , wherein the VFET fin structure comprises multiple cross fins interconnecting the first fin and the second fin.

18. The VFET fin structure of claim 16 , wherein the fin structure comprises a first cross fin interconnecting the first fin and the second fin at one end of the first fin and the second fin, and a second cross fin interconnecting the first fin and the second fin at another end of the first fin and the second fin in an O-shaped fin structure.

19. A VFET device, comprising:

a fin structure patterned in a substrate, the fin structure comprising a first fin adjacent to a second fin, and at least one cross fin interconnecting the first fin and the second fin;

bottom source and drains in the substrate beneath the fin structure;

bottom spacers disposed on the bottom source and drains;

a gate surrounding the fin structure over the bottom spacers;

top spacers disposed above the gate; and

top source and drains at a top of the fin structure.

20. The VFET device of claim 19 , wherein the at least one cross fin is oriented orthogonal to the first fin and the second fin and interconnects the first fin and the second fin at a center of the first fin and the second fin in an H-shaped fin structure.