Memory cell with asymmetric word line and erase gate for decoupled program erase performance
A memory cell, e.g., a flash memory cell, includes a substrate, a floating gate formed over the substrate, and a word line and an erase gate formed over the floating gate. The word line overlaps the floating gate by a first lateral overlap distance, and the erase gate overlaps the floating gate by a second lateral overlap distance that is substantially greater than the first lateral distance. This configuration allows the program and erase coupling to the floating gate to be optimized independently, e.g., to decrease or minimize the program current and/or increase or maximize the erase current for the cell.
1. A method of forming a memory cell, the method comprising:
forming a floating gate over a substrate;
forming a word line over the floating gate such that the word line overlaps the floating gate by a first lateral distance; and
forming an erase gate over the floating gate such that the erase gate overlaps the floating gate by a second lateral distance that is at least twice as large as the first lateral distance.
2. The method of claim 1 , wherein the memory cell comprises a flash memory cell.
3. The method of claim 1 , comprises forming a pair of floating gates of the memory cell, and forming a word line and erase gate over each floating gate,
wherein for each floating gate, the respective word line overlaps the respective floating gate by a first respective lateral distance and the respective erase gate overlaps the respective floating gate by a second respective lateral distance that is at least twice as large as the first respective lateral distance.
4. The method of claim 3 , wherein the erase gates for the pair of floating gates are provided by a shared gate.
5. The method of claim 1 , wherein the word line and the erase gate are formed in a common poly layer.
6. The method of claim 1 , wherein the floating gate is formed in a poly1 layer, and the word line and erase gate are formed in a poly2 layer.
7. The method of claim 1 , wherein the second lateral distance is at least 5 times as large as the first lateral distance.
8. The method of claim 1 , wherein, for a defined voltage level, the program current for the word line is at least 100 times as the program current for the erase gate or for a memory cell with symmetrical word line/erase gate overlap over the floating gate.
9. The method of claim 1 , wherein, for a defined voltage level, the program current for the word line is at least 1,000 times as the program current for the erase gate or for a memory cell with symmetrical word line/erase gate overlap over the floating gate.
10. A memory cell, comprising:
a substrate;
a floating gate formed over the substrate; and
a word line and an erase gate formed over the floating gate;
wherein the word line overlaps the floating gate by a first lateral distance, and the erase gate overlaps the floating gate by a second lateral distance that is at least twice as large as the first lateral distance.
11. The memory cell of claim 10 , wherein the memory cell comprises a flash memory cell.
12. The memory cell of claim 10 , wherein the memory cell includes:
a pair of floating gates, and
a word line and an erase gate over each floating gate,
wherein for each floating gate, the respective word line overlaps the respective floating gate by a first respective lateral distance and the respective erase gate overlaps the respective floating gate by a second respective lateral distance that is at least twice as large as the first respective lateral distance.
13. The memory cell of claim 12 , wherein the erase gates for the pair of floating gates are provided by a shared gate.
14. The memory cell of claim 10 , wherein the word line and the erase gate comprises portions of a common poly layer.
15. The memory cell of claim 10 , wherein the floating gate comprises a portion of a poly1 layer, and the word line and erase gate comprise portions of a poly2 layer.
16. The memory cell of claim 10 , wherein the second lateral distance is at least 5 times as large as the first lateral distance.
17. The memory cell of claim 10 , wherein, for a defined voltage level, the program current for the word line is at least 100 times as large as the program current for the erase gate or for a memory cell with symmetrical word line/erase gate overlap over the floating gate.
18. The memory cell of claim 10 , wherein, for a defined voltage level, the program current for the word line is at least 1,000 times as large as the program current for the erase gate or for a memory cell with symmetrical word line/erase gate overlap over the floating gate.
19. A memory cell, comprising:
a substrate;
a floating gate formed over the substrate; and
a word line and an erase gate formed in a common poly layer over the floating gate;
wherein the word line overlaps the floating gate by a first lateral distance, and the erase gate overlaps the floating gate by a second lateral distance that is at least twice as large as the first lateral distance.
20. The memory cell of claim 19 , wherein the floating gate comprises a portion of a poly1 layer, and the word line and erase gate comprise portions of a poly2 layer.
21. The memory cell of claim 19 , wherein the second lateral distance is at least five times as large as the first lateral distance.
22. The memory cell of claim 19 , wherein, for a defined voltage level, the program current for the word line is at least 100 times as the program current for the erase gate or for a memory cell with symmetrical word line/erase gate overlap over the floating gate.
23. A memory cell, comprising:
a pair of floating gates formed over a substrate;
a respective word line overlapping each floating gate by a respective word line lateral overlap distance; and
a shared gate located between and extending over both of the floating gates such that such that the shared gate overlaps each floating gate by a respective shared gate lateral overlap distance;
wherein for each floating gate, the respective shared gate lateral overlap distance is at least twice as large as the respective word line lateral overlap distance.
24. The memory cell of claim 23 , wherein the shared gate defines a shared erase gate for performing erase functions for each floating gate.
25. The memory cell of claim 23 , wherein the pair of word lines and the shared gate comprise portions of a common poly layer.
26. The memory cell of claim 23 , wherein for each floating gate, the respective shared gate lateral overlap distance is at least five times as large as the respective word line lateral overlap distance.