Multiple wafers fabrication technique on large carrier with warpage control stiffener
View Patent ↗Disclosed is a method of manufacturing a semiconductor device that includes adhering a plurality of semiconductor substrates and a framing member to a supporting surface of a carrier substrate. The semiconductor substrates can be wafers that can be diced or cut into a plurality of dies. Thus, the wafers each have respective active surfaces and at least one respective integrated circuit region. The method can further include encapsulating the framing member and the plurality of semiconductor substrates within an encapsulant. Subsequently, the carrier substrate is removed and a redistribution layer (RDL) is formed on the semiconductor substrates and the framing member.
1. A method of manufacturing a semiconductor device, comprising:
providing a plurality of semiconductor substrates, each having a respective active surface and at least one respective integrated circuit region, and each being configured for being cut into respective groups of dies such that the plurality of semiconductor substrates can be cut into a plurality of groups of dies;
adhering the plurality of semiconductor substrates to a supporting surface of a carrier substrate;
adhering a framing member to the supporting surface of the carrier substrate;
encapsulating the framing member and the plurality of semiconductor substrates within an encapsulant, thereby resulting in a multi-wafer encapsulated layer;
removing the carrier substrate from the multi-wafer encapsulated layer; and
forming a redistribution layer (RDL) on the semiconductor substrates of the multi-wafer encapsulated layer, thereby resulting in a multi-wafer panel.
2. The method of claim 1 , wherein the carrier substrate has a coefficient of thermal expansion (CTE) that substantially matches a CTE of the plurality of semiconductor substrates.
3. The method of claim 1 , wherein the framing member has a coefficient of thermal expansion (CTE) that substantially matches a CTE of the plurality of semiconductor substrates.
4. The method of claim 1 , wherein at least a portion of the framing member extends along the supporting surface of the carrier substrate between at least two of the plurality of semiconductor substrates.
5. The method of claim 1 , further comprising dicing the multi-wafer panel into separate dies that include the plurality of groups of dies.
6. The method of claim 1 , wherein each of the plurality of semiconductor substrates comprises silicon.
7. The method of claim 6 , wherein the framing member has a coefficient of thermal expansion (CTE) that substantially matches a CTE of silicon.
8. A method of manufacturing a semiconductor device, comprising:
providing first and second semiconductor substrates, each having a respective active surface and at least one respective integrated circuit region, the first semiconductor substrate being configured for being cut into a first group of dies and the second semiconductor substrate being configured for being cut into a second group of dies;
adhering the first and second semiconductor substrates to a supporting surface of a carrier substrate;
adhering a framing member to the supporting surface of the carrier substrate, wherein at least a portion of the framing member extends between the first and second semiconductor substrates;
encapsulating the framing member and the first and second semiconductor substrates within an encapsulant, thereby resulting in a multi-wafer encapsulated layer, wherein at least a portion of the encapsulant forms an encapsulant channel between the framing member and at least one of the first and second semiconductor substrates;
removing the carrier substrate from the multi-wafer encapsulated layer;
forming a redistribution layer (RDL) on the first and second semiconductor substrates of the multi-wafer encapsulated layer. thereby resulting in a multi-wafer panel.
9. The method of claim 8 , wherein the carrier substrate has a coefficient of thermal expansion (CTE) that substantially matches a CTE of the first and second semiconductor substrates.
10. The method of claim 8 , wherein the framing member has a coefficient of thermal expansion (CTE) that substantially matches a CTE of the first and second semiconductor substrates.
11. The method of claim 8 , wherein at least a portion of the framing member extends along the supporting surface of the carrier between the first and second semiconductor substrates.
12. The method of claim 8 , further comprising dicing the multi-wafer panel into separate dies that include the first and second groups of dies.
13. The method of claim 8 , wherein each of the first and second semiconductor substrates comprises silicon.
14. The method of claim 13 , wherein the framing member has a coefficient of thermal expansion (CTE) that substantially matches a CTE of silicon.
15. A method of manufacturing a semiconductor device, comprising:
providing a framing member that defines first and second through-holes thereof;
adhering the framing member to a supporting surface of a carrier substrate;
adhering first and second semiconductor substrates to the supporting surface of the carrier substrate respectively through the first and second through-holes of the framing member, wherein the first semiconductor substrate is configured for being cut into a first group of dies and the second semiconductor substrate is configured for being cut into a second group of dies;
encapsulating the framing member and the first and second semiconductor substrates within an encapsulant, thereby resulting in a multi-wafer encapsulated layer, wherein at least a portion of the encapsulant forms an encapsulant channel between the framing member and at least one of the first and second semiconductor substrates;
removing the carrier substrate from the multi-wafer encapsulated layer; and
forming a redistribution layer (RDL) on the first and second semiconductor substrates of the multi-wafer encapsulated layer, thereby resulting in a multi-wafer panel.
16. The method of claim 15 , wherein the carrier substrate has a coefficient of thermal expansion (CTE) that substantially matches a CTE of the first and second semiconductor substrates.
17. The method of claim 15 , wherein the framing member has a coefficient of thermal expansion (CTE) that substantially matches a CTE of the first and second semiconductor substrates.
18. The method of claim 15 , further comprising dicing the multi-wafer panel into separate dies that include the first and second groups of dies.
19. The method of claim 15 , wherein each of the first and second semiconductor substrates comprises silicon.
20. The method of claim 19 , wherein the framing member has a coefficient of thermal expansion (CTE) that substantially matches a CTE of silicon.