IP Library › Granted Patent US 10,825,853
Granted Patent B2
US 10,825,853 · App. 15/937,210 · Granted Nov 3, 2020

Semiconductor image sensor device with deep trench isolations and method for manufacturing the same

Inventors: Yen-Ting Chiang (Tainan, TW); Chun-Yuan Chen (Tainan, TW); Hsiao-Hui Tseng (Tainan, TW); Sheng-Chan Li (Tainan, TW); Yu-Jen Wang (Kaohsiung, TW); Wei Chuang Wu (Tainan, TW); Shyh-Fann Ting (Tainan, TW); Jen-Cheng Liu (Hsin-Chu, TW); Dun-Nian Yaung (Taipei, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
H01L27/1463H01L27/14687H01L27/14689H01L27/1464H01L27/14643
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Quick Facts
Patent No.
US 10,825,853
App. No.
15/937,210
Granted
Nov 3, 2020
Kind
B2
Abstract

A semiconductor image sensor device includes a semiconductor substrate, a radiation-sensing region, and a first isolation structure. The radiation-sensing region is in the semiconductor substrate. The first isolation structure is in the semiconductor substrate and adjacent to the radiation-sensing region. The first isolation structure includes a bottom isolation portion in the semiconductor substrate, an upper isolation portion in the semiconductor substrate, and a diffusion barrier layer surrounding a sidewall of the upper isolation portion.

Claims (48)

1. A semiconductor image sensor device, comprising:

a semiconductor substrate including a first surface and a second surface opposite to the first surface;

a radiation-sensing region in the semiconductor substrate;

an interconnection structure over the first surface of the semiconductor substrate, wherein the interconnection structure comprises a dielectric layer and at least a conductive structure in the dielectric layer;

a color filter disposed over the second surface of the semiconductor substrate;

a first isolation structure in the semiconductor substrate and adjacent to the radiation-sensing region, wherein the first isolation structure comprises:

a bottom isolation portion in the semiconductor substrate;

an upper isolation portion in the semiconductor substrate; and

a diffusion barrier layer surrounding a sidewall of the upper isolation portion, wherein a sidewall of the bottom isolation portion is uncovered by the diffusion barrier layer,

wherein the upper isolation portion of the first isolation structure is extended from the semiconductor substrate into the dielectric layer of the interconnection structure over the semiconductor substrate and a top surface of the upper isolation portion of the first isolation structure is in contact with the dielectric layer of the interconnection structure.

2. The semiconductor image sensor device of claim 1 , wherein the semiconductor substrate has a first doping polarity, and the radiation-sensing region has a second doping polarity opposite to the first doping polarity.

3. The semiconductor image sensor device of claim 2 , further comprising a doped layer surrounding the sidewall of the bottom isolation portion, wherein the doped layer has the first doping polarity.

4. The semiconductor image sensor device of claim 1 , wherein the first isolation structure surrounds a periphery of the radiation-sensing region.

5. The semiconductor image sensor device of claim 1 , wherein a depth of the first isolation structure is equal to or greater than a depth of the radiation-sensing region.

6. The semiconductor image sensor device of claim 1 , wherein a width of the upper isolation portion of the first isolation structure is equal to a width of the bottom isolation portion of the first isolation structure.

7. The semiconductor image sensor device of claim 1 , further comprising a second isolation structure in the semiconductor substrate, wherein a depth of the second isolation structure is less than a depth of the first isolation structure.

8. A semiconductor image sensor device, comprising:

a semiconductor substrate having a first doping polarity;

a radiation-sensing region in the semiconductor substrate, wherein the radiation-sensing region has a second doping polarity, and an interface between the radiation-sensing region and the semiconductor substrate form a PN junction;

a first isolation structure in the semiconductor substrate;

a second isolation structure in the semiconductor substrate and separated from the first isolation structure, wherein a depth of the second isolation structure is less than a depth of the first isolation structure;

a dielectric layer over the semiconductor substrate;

a conductive structure in and over the dielectric layer, wherein the conductive structure is disposed between the first isolation structure and the second isolation structure, surrounded by the first isolation structure and the second isolation structure from a top view, and separated from the first isolation structure and the second isolation structure;

a doped layer in the semiconductor substrate and surrounding a sidewall of a first isolation portion of the first isolation structure, wherein the doped layer has the first doping polarity; and

a diffusion barrier layer in the semiconductor substrate and surrounding a sidewall of a second isolation portion of the first isolation structure,

wherein the sidewall of the first isolation portion is uncovered by the diffusion barrier layer, the sidewall of the second isolation portion is uncovered by the doped layer, and a depth of the second isolation portion is less than the depth of the second isolation structure,

wherein the second isolation portion of the first isolation structure is exposed to the dielectric layer over the semiconductor substrate.

9. The semiconductor image sensor device of claim 8 , wherein the diffusion barrier layer is conformal with respect to the sidewall of the second isolation portion of the first isolation structure.

10. The semiconductor image sensor device of claim 8 , wherein the diffusion barrier layer is a single-layered diffusion barrier layer, and a material of the diffusion barrier layer comprises an oxide compound, a nitride compound, an oxynitride compound, or a combination thereof.

11. The semiconductor image sensor device of claim 8 , wherein the diffusion barrier layer is a multi-layered diffusion barrier layer comprising a plurality of barrier films, and a material of each barrier film individually comprises an oxide compound, a nitride compound, an oxynitride compound, or a combination thereof.

12. The semiconductor image sensor device of claim 8 , wherein the first isolation structure surrounds a periphery of the radiation-sensing region.

13. The semiconductor image sensor device of claim 8 , wherein the depth of the first isolation structure is equal to or greater than a depth of the radiation-sensing region.

14. The semiconductor image sensor device of claim 8 , wherein a width of the second isolation portion is equal to a width of the first isolation portion.

15. The semiconductor image sensor device of claim 8 , wherein a width of the second isolation structure is less than a width of the first isolation structure.

16. A semiconductor image sensor device, comprising:

a semiconductor substrate;

a radiation-sensing region in the semiconductor substrate, wherein an interface between the radiation-sensing region and the semiconductor substrate form a PN junction;

a deep trench isolation structure in the semiconductor substrate and adjacent to the radiation-sensing region;

a doped layer between the semiconductor substrate and a first portion of the deep trench isolation structure, wherein the doped layer has a same doping polarity as the semiconductor substrate, a doping concentration of the doped layer is higher than that of the semiconductor substrate, and the doped layer is in contact with a sidewall of the first portion of the deep trench isolation structure;

a diffusion barrier layer between the semiconductor substrate and a sidewall of a second portion of the deep trench isolation structure;

a shallow trench isolation structure in the semiconductor substrate, wherein the shallow trench isolation structure is extended from a first surface towards a second surface of the semiconductor substrate, and a depth of the second portion of the deep trench isolation structure is less than a depth of the shallow trench isolation structure;

a dielectric layer over the semiconductor substrate; and

a conductive structure in and over the dielectric layer, wherein the conductive structure is disposed between the deep trench isolation structure and the shallow trench isolation structure, surrounded by the deep trench isolation structure and the shallow trench isolation structure from a top view, and separated from the deep trench isolation structure and the shallow trench isolation structure,

wherein the first portion of the deep trench isolation structure is disposed in the semiconductor substrate and the second portion of the deep trench isolation structure is disposed in the semiconductor substrate and further extended into the dielectric layer over the semiconductor substrate.

17. The semiconductor image sensor device of claim 16 , wherein a depth of the deep trench isolation structure is equal to or greater than a depth of the radiation-sensing region.

18. The semiconductor image sensor device of claim 16 , wherein the deep trench isolation structure surrounds the radiation-sensing region.

19. The semiconductor image sensor device of claim 16 , wherein the deep trench isolation structure and the shallow trench isolation structure are extended from the first surface towards the second surface of the semiconductor substrate.

20. The semiconductor image sensor device of claim 16 , wherein a first portion of the shallow trench isolation structure is disposed in the semiconductor substrate and a second portion of the shallow trench isolation structure is disposed in the dielectric layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 28, 2018
From: CHIANG, YEN-TING; CHEN, CHUN-YUAN; TSENG, HSIAO-HUI; LI, SHENG-CHAN; WANG, YU-JEN; WU, WEI CHUANG; TING, SHYH-FANN; LIU, JEN-CHENG; YAUNG, DUN-NIAN
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Reel/Frame 045372/0692 →
Continuity (2)
Provisional Application 62583906 · Nov 9, 2017
Related Publication 20190139997A1 · May 9, 2019
Cited By (3)
US 12,205,970 US 12,288,797 US 12,713,727