Granted Patent B1

US 10,360,164 · App. 15/944,772 · Granted Jul 23, 2019

Abstract

Claims (52)

1. A processor, comprising:

a central processing unit (CPU); and

a direct memory access (DMA) adapter circuit, wherein:

the DMA adapter circuit includes a DMA controller circuit;

the DMA adapter circuit is configured to interface with a legacy internal hardware peripheral and with a DMA-enabled internal hardware peripheral;

the DMA-enabled internal hardware peripheral includes a first special function register (SFR);

the legacy internal hardware peripheral includes no DMA features;

the CPU is configured to execute a legacy application, the legacy application configured to access a first setting in memory through the legacy internal hardware peripheral, wherein execution of the legacy application includes access by the CPU of the first setting in memory; and

the DMA controller circuit is configured to access the first setting in memory during execution of a DMA-enabled application through the DMA-enabled internal hardware peripheral.

2. The processor of claim 1 , wherein the CPU is configured to view the first setting as stored in the first SFR in a memory map.

3. The processor of claim 1 , wherein:

the first SFR is a DMA SFR;

the first setting is configured to be stored in the first SFR; and

the first SFR is not visible to the CPU.

4. The processor of claim 1 further comprising a second SFR and a third SFR in the DMA adapter circuit, wherein:

the third SFR is a DMA SFR;

the legacy internal hardware peripheral is configured to allow the CPU to access a second setting in memory stored in the second SFR during execution of the DMA-enabled application; and

the DMA-enabled internal hardware peripheral is configured to allow the DMA controller circuit to access a third setting in memory stored in the third SFR during execution of the DMA-enabled application;

the third SFR is not visible to the CPU.

5. The processor of claim 4 , wherein the second SFR and the third SFR share a same identified address.

6. The processor of claim 1 , wherein the legacy application and the DMA-enabled application are configured to access the first setting in memory at a same identified address.

7. The processor of claim 1 , wherein the legacy application is without DMA functions configured to access the first setting.

8. The processor of claim 1 , wherein the DMA controller circuit is configured to receive an event generated in the DMA-enabled application through a second SFR of the DMA-enabled internal hardware peripheral.

9. The processor of claim 8 , wherein the CPU is configured to receive an event generated by execution of the legacy application and received on a CPU interrupt bus from the legacy internal hardware peripheral.

10. A method, comprising:

determining that an internal hardware peripheral is connected to a central processing unit (CPU) and a DMA controller circuit;

determining whether the internal hardware peripheral is a legacy internal hardware peripheral or a DMA-enabled internal hardware peripheral, the DMA-enabled internal hardware peripheral to access a first special function register (SFR);

based on a determination that the internal hardware peripheral is a legacy internal hardware peripheral, executing a legacy application, wherein:

the legacy application is configured to access a first setting in memory through the legacy internal hardware peripheral; and

execution of the legacy application includes access by the CPU of the first setting in memory; and

based on a determination that the internal hardware peripheral is a DMA-enabled internal hardware peripheral, executing a DMA-enabled application, wherein:

the DMA-enabled application is configured to access the first setting in memory through the DMA-enabled internal hardware peripheral; and

execution of the legacy application includes the CPU accessing the first setting in memory with the DMA controller circuit.

11. The method of claim 10 , further comprising:

storing the first setting in the first SFR;

including the first SFR in a memory map; and

viewing, from the CPU, the first setting as stored in the first SFR in a memory map.

12. The method of claim 10 , wherein:

the first SFR is a DMA SFR;

the first setting is configured to be stored in the first SFR; and

the first SFR is not visible to the CPU.

13. The method of claim 10 , further comprising:

accessing, by the CPU, a second SFR;

accessing, by the controller circuit, a third SFR, wherein the third SFR is a DMA SFR;

allowing access from the CPU to a second setting stored in the second SFR during execution of the DMA-enabled application; and

allowing access from the DMA controller circuit to a third setting in the third SFR during execution of the DMA-enabled application;

wherein the third SFR is not visible to the CPU.

14. The method of claim 13 , wherein the second SFR and the third SFR share a same identified address.

15. The method of claim 10 , further comprising accessing, with the legacy application and the DMA-enabled application, the first setting in memory at a same identified address.

16. The method of claim 10 , further comprising executing the legacy application without DMA functions to access the first setting.

17. The method of claim 10 , further comprising receiving an event generated in the DMA-enabled application through a second SFR of the DMA-enabled internal hardware peripheral.

18. The method of claim 10 , further comprising receiving an event through the CPU, the event generated in the legacy application and received on a CPU interrupt bus from the legacy internal hardware peripheral.

Assignments (13)