Method for fabricating semiconductor device
A semiconductor device including a logic transistor, a non-volatile memory (NVM) cell and a contact etching stop layer (CESL) is shown. The CESL includes a first silicon nitride layer on the logic transistor but not on the NVM cell, a silicon oxide layer on the first silicon nitride layer and on the NVM cell, and a second silicon nitride layer disposed on the silicon oxide layer over the logic transistor and disposed on the silicon oxide layer on the NVM cell.
1. A method for fabricating a semiconductor device, comprising:
providing a substrate having a logic transistor and a non-volatile memory (NVM) cell thereon; and
forming a contact etching stop layer (CESL), comprising:
forming a first silicon nitride layer on the logic transistor but not on the NVM cell;
forming a silicon oxide layer on the first silicon nitride layer and on the NVM cell; and
forming a second silicon nitride layer on the silicon oxide layer over the logic transistor, and also on the silicon oxide layer on the NVM cell.
2. The method device of claim 1 , wherein the NVM cell comprises a single-poly non-volatile memory (SPNVM) cell.
3. The method of claim 1 , wherein the NVM cell comprises a memory cell comprising a charge trapping layer.
4. The method of claim 3 , wherein the charge trapping layer comprises a silicon nitride film.
5. The method of claim 4 , wherein the memory cell comprising the charge trapping layer comprises a silicon/oxide/nitride/oxide/silicon (SONOS) cell.
6. The method of claim 1 , wherein the NVM cell comprises a memory cell having a stack of a floating gate and a control gate.
7. The method of claim 1 , wherein
a self-aligned silicide (salicide) layer has been formed on the logic transistor and the NVM cell on the provided substrate,
the first silicon nitride layer is also formed on the salicide layer formed on the logic transistor, and
the silicon oxide layer is also formed on the salicide layer formed on the NVM cell.