Sensing amplifier comprising fully depleted silicon-on-insulator transistors for reading a selected flash memory cell in an array of flash memory cells
View Patent ↗The present invention relates to a flash memory system comprising one or more sense amplifiers for reading data stored in flash memory cells. The sense amplifiers utilize fully depleted silicon-on-insulator transistors to minimize leakage. The fully depleted silicon-on-insulator transistors comprise one or more fully depleted silicon-on-insulator NMOS transistors and/or one or more fully depleted silicon-on-insulator PMOS transistors.
1. A flash memory system comprising:
an array of flash memory cells; and
a sensing amplifier for reading a selected memory cell in the array of flash memory cells, the sensing amplifier comprising:
a first stage comprising a first fully depleted silicon-on-insulator PMOS transistor for providing a reference current to a sensing node, a first fully depleted silicon-on-insulator NMOS transistor coupled between the sensing node and a selected flash memory cell in the array;
a second stage comprising a second fully depleted silicon-on-insulator PMOS transistor for providing a reference current to a reference node, a second fully depleted silicon-on-insulator NMOS transistor coupled between the reference node and a reference flash memory cell; and
a differential amplifier for receiving the sensing node and the reference node as inputs and generating an output indicative of a value stored in the selected flash memory cell.
2. The flash memory system of claim 1 , wherein the selected memory cell is in a first plane of the array and the reference memory cell is in a second plane of the array.
3. The flash memory system of claim 2 , wherein the first plane provides a selected bitline coupled to the selected memory cell and the second plane provides another selected bitline coupled to the reference memory cell.
4. The flash memory system of claim 2 , wherein a forward body bias is used in active mode and a reverse body bias is used in a standby mode for the first and second fully depleted silicon-on-insulator PMOS transistors and the first and second fully depleted silicon-on-insulator NMOS transistors.
5. The flash memory system of claim 4 , wherein the forward body bias or reverse body bias is used to reduce an offset of the sense amplifier.
6. The flash memory system of claim 1 , wherein the first and second fully depleted silicon-on-insulator PMOS transistors each comprises a p-well biased to ground and the first and second fully depleted silicon-on-insulator NMOS transistors each comprises an n-well biased to ground.
7. The flash memory system of claim 1 , wherein the memory cells comprise source side injection flash memory cells, each comprising:
an erase gate to provide erasing;
a coupling gate; and
a source line to provide programming current.
8. The flash memory system of claim 1 , wherein the first and second fully depleted silicon-on-insulator PMOS transistors each comprises a p-well coupled to a first variable voltage source and the first and second fully depleted silicon-on-insulator NMOS transistors each comprises an n-well coupled to a second variable voltage source.
9. A flash memory sensing system comprising:
an array of flash memory cells; and
a sensing amplifier for reading a selected memory cell in the array of flash memory cells, the sensing amplifier comprising:
a first stage comprising a first bulk CMOS transistor comprising a first fully depleted silicon-on-insulator PMOS transistor and a first fully depleted silicon-on-insulator NMOS transistor, wherein a sensing node is formed between the first fully depleted silicon-on-insulator PMOS transistor and the first fully depleted silicon-on-insulator NMOS transistor and the first fully depleted silicon-on-insulator NMOS transistor is coupled to a selected flash memory cell in the array;
a second stage comprising a second bulk CMOS transistor comprising a second fully depleted silicon-on-insulator PMOS transistor and a second fully depleted silicon-on-insulator NMOS transistor, wherein a reference node is formed between the second fully depleted silicon-on-insulator PMOS transistor and the second fully depleted silicon-on-insulator NMOS transistor and the second fully depleted silicon-on-insulator NMOS transistor is coupled to a reference memory cell; and
a differential amplifier for receiving the sensing node and the reference node as inputs and generating an output indicative of a value stored in the selected flash memory cell.
10. The flash memory sensing system of claim 9 , wherein the first fully depleted silicon-on-insulator PMOS transistor is coupled to a first power supply and the second fully depleted silicon-on-insulator PMOS transistor is coupled to a second power supply, wherein the first power supply has a higher voltage than the second power supply.
11. The flash memory sensing system of claim 9 , wherein the differential amplifier comprises latched inverters.
12. The flash memory sensing system of claim 11 , wherein the latched inverters are coupled to NMOS input pairs that are coupled to the sensing node.
13. A flash memory system comprising:
an array of flash memory cells arranges into rows and columns; and
a row decoder for selecting a row of flash memory cells in the array for a read or write operation, the row decoder comprising one or more fully depleted silicon-on-insulator NMOS transistors, and one or more fully depleted silicon-on-insulator PMOS transistors;
a column decoder for selecting a column of flash memory cells in the array for a read or write operation, the column decoder comprising one or more fully depleted silicon-on-insulator NMOS transistors each comprising a p-well under a buried oxide layer, and one or more fully depleted silicon-on-insulator NMOS transistors each comprising an n-well under a buried oxide layer; and
a sensing amplifier comprising:
a first stage comprising a first fully depleted silicon-on-insulator PMOS transistor for providing a reference current to a sensing node, a first fully depleted silicon-on-insulator NMOS transistor coupled between the sensing node and a selected flash memory cell in the array;
a second stage comprising a second fully depleted silicon-on-insulator PMOS transistor for providing a reference current to a reference node, a second fully depleted silicon-on-insulator NMOS transistor coupled between the reference node and a reference flash memory cell; and
a differential amplifier for receiving the sensing node and the reference node as inputs and generating an output indicative of a value stored in the selected flash memory cell.
14. The flash memory system of claim 13 , wherein each flash memory cell comprises:
an erase gate to provide erasing;
a coupling gate; and
a source line to provide programming current.
15. The flash memory system of claim 13 , wherein the array comprises a plurality of flash sub-arrays, each comprising separate p-wells underneath.
16. A flash memory system comprising:
an array of flash memory cells arranges into rows and columns;
a row decoder for selecting a row of flash memory cells in the array for a read or write operation, the row decoder comprising one or more fully depleted silicon-on-insulator NMOS transistors, and one or more fully depleted silicon-on-insulator PMOS transistors;
a column decoder for selecting a column of flash memory cells in the array for a read or write operation, the column decoder comprising one or more fully depleted silicon-on-insulator NMOS transistors each comprising a p-well under a buried oxide layer, and one or more fully depleted silicon-on-insulator NMOS transistors each comprising an n-well under a buried oxide layer;
a sensing amplifier for reading a selected memory cell in the array of flash memory cells, the sensing amplifier comprising one or more fully depleted silicon-on-insulator NMOS transistors, and one or more fully depleted silicon-on-insulator PMOS transistors; and
a high voltage decoder comprising:
an erase gate decoder for providing a high voltage to an erase gate terminal of a selected flash memory cell;
a coupling gate decoder for providing a high voltage a coupling gate terminal of a selected flash memory cell; and
a sourceline decoder for providing a high voltage to a sourceline terminal of a selected flash memory cell.
17. The flash memory system of claim 16 , wherein the high voltage decoder further comprises an enabling latch comprising fully depleted silicon-on-insulator transistors.
18. The flash memory system of claim 16 , wherein the erase gate decoder, the coupling gate decoder, and the source line decoder each comprises bulk CMOS transistors.