Access to DRAM through a reuse of pins
An apparatus includes an interface for dynamic random access memory (DRAM); and an integrated circuit. The integrated circuit includes a memory pinout configured to connect to the memory and control logic. The control logic is configured multiplex address information, command information, and data to be written to or read from the DRAM memory on a subset of pins of the memory pinout to the DRAM memory. The control logic is further configured to route other signals on other pins of the memory pinout to the DRAM in parallel with the multiplexed address information, command information, and data information.
1. An apparatus, comprising:
an interface for dynamic random access memory (DRAM); and
an integrated circuit including:
a memory pinout configured to connect to the DRAM memory; and
control logic circuit configured to:
multiplex address information, command information, and data to be written to or read from the DRAM memory on a subset of pins of the memory pinout to the DRAM memory; and
route other signals on other pins of the memory pinout to the DRAM memory in parallel with the multiplexed address information, command information, and data information;
wherein the command information is configured to cause the DRAM memory to:
in first cycle, load initial address information;
in a second cycle subsequent to the first cycle:
use implicit address information derived from the initial address information;
write or read data using pins that held the initial address information in the first cycle.
2. The apparatus of claim 1 , wherein the command information is configured to cause the DRAM memory to ignore input pins of the DRAM memory configured to receive data to be written to the DRAM memory.
3. The apparatus of claim 1 , wherein the initial address information is provided at a location before a desired address location for the write of data.
4. The apparatus of claim 1 , wherein the control logic circuit is configured to multiplex address information, command information and data to be written to or read from the DRAM memory by:
sending command and address information in the first cycle to the DRAM memory on a set of pins; and
sending or receiving data to be written to or read from the DRAM memory in the second cycle on the set of pins.
5. The apparatus of claim 1 , wherein the control logic circuit is configured to multiplex address information, command information and data to be written to or read from the DRAM memory by:
sending command and address information in the first cycle to the DRAM memory, wherein the command information configures the DRAM memory to ignore input data pins in the first cycle.
6. The apparatus of claim 1 , wherein the control logic circuit is configured to multiplex address information, command information and data to be written to or read from the DRAM memory by:
in the first cycle, routing command information and address information from a same set of pins on the integrated circuit as data to be written to or read from the DRAM memory;
wherein the command information configures the DRAM memory to ignore input data received at the DRAM memory from the set of pins on the integrated circuit.
7. The apparatus of claim 1 , wherein the control logic circuit is configured to multiplex address information, command information and data to be written to or read from the DRAM memory by:
routing command information and address information from a same set of pins on the integrated circuit as data to be written to or read from the DRAM memory;
wherein a data pin on the DRAM memory and a command pin on the DRAM memory are connected to a same given pin on the integrated circuit, the given pin a member of the set of pins.
8. The apparatus of claim 1 , wherein the command information to be multiplexed with the data to be written to or read from the DRAM memory includes one or more of a column address strobe command, a row address strobe command, and a write enable command.
9. The apparatus of claim 1 , wherein the control logic circuit is configured to multiplex address information, command information and data to be written to or read from the DRAM memory by:
using a data mask to instruct the DRAM memory to ignore present values on data input pins of the DRAM memory;
set reading or writing of data to continuous burst mode; and
set an address to a location previous to an intended write location or an intended read location.
10. A method, comprising:
from an integrated circuit, accessing a dynamic random access memory (DRAM) using a memory pinout on the integrated circuit;
multiplexing address information, command information, and data to be written to or read from the DRAM memory on a subset of pins of the memory pinout to the DRAM memory; and
routing other signals on other pins of the memory pinout to the DRAM memory in parallel with the multiplexed address information, command information, and data information;
wherein the command information causes the DRAM memory to:
in first cycle, load initial address information; and
in a second cycle subsequent to the first cycle:
use implicit address information derived from the initial address information; and
write or read data using pins that held the initial address information in the first cycle.
11. The method of claim 10 , wherein the command information is configured to cause the DRAM memory to ignore input pins of the DRAM memory configured to receive data to be written to the DRAM memory.
12. The method of claim 10 , wherein the initial address information is provided at a location before a desired address location for the write of data.
13. The method of claim 10 , further comprising multiplexing address information, command information and data to be written to or read from the DRAM memory by:
sending command and address information in the first cycle to the DRAM memory on a set of pins; and
sending or receiving data to be written to or read from the DRAM memory in the second cycle on the set of pins.
14. The method of claim 10 , further comprising multiplexing address information, command information and data to be written to or read from the DRAM memory by:
sending command and address information in the first cycle to the DRAM memory, wherein the command information configures the DRAM memory to ignore input data pins in the first cycle.
15. The method of claim 10 , further comprising multiplexing address information, command information and data to be written to or read from the DRAM memory by:
in the first cycle, routing command information and address information from a same set of pins on the integrated circuit as data to be written to or read from the DRAM memory;
wherein the command information configures the DRAM memory to ignore input data received at the DRAM memory from the set of pins on the integrated circuit.
16. The method of claim 10 , further comprising multiplexing address information, command information and data to be written to or read from the DRAM memory by:
routing command information and address information from a same set of pins on the integrated circuit as data to be written to or read from the DRAM memory;
wherein a data pin on the DRAM memory and a command pin on the DRAM memory are connected to a same given pin on the integrated circuit, the given pin a member of the set of pins.
17. The method of claim 10 , further comprising multiplexing address information, command information and data to be written to or read from the DRAM memory by:
using a data mask to instruct the DRAM memory to ignore present values on data input pins of the DRAM memory;
set reading or writing of data to continuous burst mode; and
set an address to a location previous to an intended write location or an intended read location.
18. A microcontroller, comprising:
a dynamic random access memory (DRAM); and
a memory pinout configured to connect to the DRAM memory; and
control logic circuit configured to:
multiplex address information, command information, and data to be written to or read from the DRAM memory on a subset of pins of the memory pinout to the DRAM memory; and
route other signals on other pins of the memory pinout to the DRAM memory in parallel with the multiplexed address information, command information, and data information;
wherein the command information is configured to cause the DRAM memory to:
in first cycle, load initial address information; and
in a second cycle subsequent to the first cycle:
use implicit address information derived from the initial address information; and
write or read data using pins that held the initial address information in the first cycle.