IP Library Granted Patent US 10,466,851
Granted Patent B2
US 10,466,851 · App. 15/962,529 · Granted Nov 5, 2019

Connecting electrodes to voltages

Inventors: Trond Jarle Pedersen (Jarle, NO); Torgeir Fenheim (Mo I Rana, NO); Jan Rune Herheim (Trondheim, NO); Stefan Markus Schabel (Syrgenstein, DE)
Assignee: Atmel Corporation
G06F3/044G06F1/3262G06F3/0416G06F2203/04107
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Quick Facts
Patent No.
US 10,466,851
App. No.
15/962,529
Granted
Nov 5, 2019
Kind
B2
Abstract

In one embodiment, an apparatus includes a first electrode, one or more processors, and one or more memory units coupled to the one or more processors. The one or more memory units collectively store logic that is configured to cause the one or more processors to control connections of the first electrode by connecting the first electrode to a first reference voltage, then connecting the first electrode to a second reference voltage lower than the first reference voltage, and then connecting the first electrode to a third reference voltage lower than the first reference voltage and the second reference voltage. The second reference voltage is coupled to a capacitor.

Claims (54)

1. An apparatus, comprising:

a first electrode;

one or more processors; and

one or more memory units coupled to the one or more processors, the one or more memory units collectively storing logic configured, when executed by the one or more processors, to cause the one or more processors to control connections of the first electrode by:

connecting the first electrode to a first reference voltage;

after connecting the first electrode to the first reference voltage, connecting the first electrode to a second reference voltage, wherein a capacitor is coupled to the second reference voltage and the second reference voltage is lower than the first reference voltage;

after connecting the first electrode to the second reference voltage, connecting the first electrode to a third reference voltage, wherein the third reference voltage is lower than the first reference voltage and the second reference voltage;

connecting the first electrode to a fourth reference voltage prior to connecting the first electrode to the first reference voltage, wherein the fourth reference voltage is lower than the first reference voltage and higher than the third reference voltage; and

after connecting the first electrode to the second reference voltage and prior to connecting the first electrode to the third reference voltage, connecting the first electrode to a fifth reference voltage, wherein the fifth reference voltage is lower than the second reference voltage and higher than the third reference voltage.

2. The apparatus of claim 1 , wherein the capacitor is coupled to a voltage supply of a circuit.

3. The apparatus of claim 1 , wherein the capacitor is further coupled to a bleed circuit configured to discharge excess charge stored in the capacitor.

4. The apparatus of claim 3 , wherein the bleed circuit comprises a comparator circuit.

5. The apparatus of claim 1 , wherein the first electrode is an electrode of a capacitive touch sensor.

6. The apparatus of claim 1 , further comprising a second electrode, wherein the logic is further configured, when executed by the one or more processors, to cause the one or more processors to control connections of the second electrode by:

connecting the second electrode to the first reference voltage while the first electrode is connected to the first reference voltage; and

connecting the second electrode to the third reference voltage while the first electrode is connected to the second reference voltage and then the third reference voltage.

7. The apparatus of claim 6 , wherein the first electrode and the second electrode are electrodes of a capacitive touch sensor.

8. The apparatus of claim 1 further comprising a second electrode, wherein the logic is further configured, when executed by the one or more processors, to cause the one or more processors to control connections of the second electrode by:

connecting the second electrode to the fourth reference while the first electrode is connected to the fourth reference voltage; and

connecting the second electrode to the fifth reference voltage while the first electrode is connected to the second reference voltage and then the fifth reference voltage.

9. The apparatus of claim 8 , wherein the first electrode and the second electrode are electrodes of a capacitive touch sensor.

10. A method, comprising:

connecting a first electrode to a first reference voltage;

after connecting the first electrode to the first reference voltage, connecting the first electrode to a second reference voltage, wherein a capacitor is coupled to the second reference voltage and the second reference voltage is lower than the first reference voltage;

after connecting the first electrode to the second reference voltage, connecting the first electrode to a third reference voltage, wherein the third reference voltage is lower than the first reference voltage and the second reference voltage;

connecting the first electrode to a fourth reference voltage prior to connecting the first electrode to the first reference voltage, wherein the fourth reference voltage is lower than the first reference voltage and higher than the third reference voltage; and

after connecting the first electrode to the second reference voltage and prior to connecting the first electrode to the third reference voltage, connecting the first electrode to a fifth reference voltage, wherein the fifth reference voltage is lower than the second reference voltage and higher than the third reference voltage.

11. The method of claim 10 , further comprising providing charge from the capacitor to a voltage supply of a circuit.

12. The method of claim 10 , further comprising discharging excess charge stored in the capacitor to a bleed circuit.

13. The method of claim 10 , further comprising:

connecting a second electrode to the first reference voltage while the first electrode is connected to the first reference voltage; and

connecting the second electrode to the third reference voltage while the first electrode is connected to the second reference voltage and then the third reference voltage.

14. The method of claim 10 , further comprising:

connecting a second electrode to the fourth reference while the first electrode is connected to the fourth reference voltage; and

connecting the second electrode to the fifth reference voltage while the first electrode is connected to the second reference voltage and then the fifth reference voltage.

15. A computer-readable non-transitory storage medium comprising logic that is configured, when executed, to:

connect a first electrode to a first reference voltage;

after connecting the first electrode to the first reference voltage, connect the first electrode to a second reference voltage, wherein a capacitor is coupled to the second reference voltage and the second reference voltage is lower than the first reference voltage;

after connecting the first electrode to the second reference voltage, connect the first electrode to a third reference voltage, wherein the third reference voltage is lower than the first reference voltage and the second reference voltage;

connect the first electrode to a fourth reference voltage prior to connecting the first electrode to the first reference voltage, wherein the fourth reference voltage is lower than the first reference voltage and higher than the third reference voltage; and

after connecting the first electrode to the second reference voltage and prior to connecting the first electrode to the third reference voltage, connect the first electrode to a fifth reference voltage, wherein the fifth reference voltage is lower than the second reference voltage and higher than the third reference voltage.

16. The computer-readable non-transitory storage medium of claim 15 , wherein the logic is further configured, when executed, to provide charge from the capacitor to a voltage supply of a circuit.

17. The computer-readable non-transitory storage medium of claim 15 , wherein the logic is further configured, when executed, to discharge excess charge stored in the capacitor to a bleed circuit.

18. The computer-readable non-transitory storage medium of claim 15 , wherein the logic is further configured, when executed, to:

connect a second electrode to the first reference voltage while the first electrode is connected to the first reference voltage; and

connect the second electrode to the third reference voltage while the first electrode is connected to the second reference voltage and then the third reference voltage.

19. The computer-readable non-transitory storage medium of claim 15 , wherein the logic is further configured, when executed, to:

connect a second electrode to the fourth reference while the first electrode is connected to the fourth reference voltage; and

connect the second electrode to the fifth reference voltage while the first electrode is connected to the second reference voltage and then the fifth reference voltage.

20. A method, comprising:

connecting a first electrode to a first reference voltage;

after connecting the first electrode to the first reference voltage, connecting the first electrode to a second reference voltage, wherein a capacitor is coupled to the second reference voltage and the second reference voltage is lower than the first reference voltage;

after connecting the first electrode to the second reference voltage, connecting the first electrode to a third reference voltage, wherein the third reference voltage is lower than the first reference voltage and the second reference voltage; and

providing charge from the capacitor to a voltage supply of a circuit.

Assignments (13)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0335 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059263/0001 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 058214/0625 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 052856/0909 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 25, 2018
From: PEDERSEN, TROND JARLE; FENHEIM, TORGEIR; HERHEIM, JAN RUNE; SCHABEL, STEFAN MARKUS
To: ATMEL CORPORATION
Reel/Frame 045634/0824 →
Continuity (2)
Continuation 15045834 · Feb 17, 2016
Related Publication 20190121462A1 · Apr 25, 2019