IP Library Granted Patent US 10,664,435
Granted Patent B2
US 10,664,435 · App. 15/970,726 · Granted May 26, 2020

Devices and methods for transmission of events with a uniform latency on serial communication links

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,664,435
App. No.
15/970,726
Granted
May 26, 2020
Kind
B2
Abstract

The present disclosure relates generally to serial communication links and, more specifically, to events communicated on serial communication links and the timing of those events, for example, to achieve uniform delay among multiple event transmissions.

Claims (43)

1. A serial communication link, comprising:

a transmitter and a receiver configured to define a uniform latency between a transmitter-side event and a receiver-side event;

the transmitter comprising:

delay circuitry configured to receive the transmitter-side event and delay the transmitter-side event by a delay time corresponding to a frame length; and

control circuitry configured to prevent additional frames from being started while the transmitter-side event is being delayed; and

transmission circuitry configured to send an event frame corresponding to the transmitter-side event after the delay time, wherein the transmission circuitry is configured to include, in the event frame, event identifier bits indicative that the frame being transmitted is an event frame; and

the receiver comprising:

receive circuitry configured to:

decode the frame being transmitted as the event frame; and

assert the receiver-side event responsive to the decoding.

2. The serial communication link of claim 1 , wherein the delay circuitry comprises a shift register of a size corresponding to a number of bits corresponding to the frame length.

3. The serial communication link of claim 1 , wherein the delay circuitry comprises a counter and a register, the counter configured to count a number corresponding to a number of bits corresponding to the frame length.

4. The serial communication link of claim 1 , wherein the transmission circuitry is configured to encode frames based on a protocol selected from a group consisting of a Universal Asynchronous Receiver/Transmitter, a Universal Synchronous Receiver/Transmitter, or a Universal Synchronous/Asynchronous Receiver/Transmitter.

5. The serial communication link of claim 1 , wherein the receive circuitry is configured to decode frames based on a protocol selected from a group consisting of a Universal Asynchronous Receiver/Transmitter, a Universal Synchronous Receiver/Transmitter, or a Universal Synchronous/Asynchronous Receiver/Transmitter.

6. The serial communication link of claim 1 , wherein the delay time is as long as one frame length.

7. The serial communication link of claim 1 , wherein a duration of the uniform latency is a fixed delay specified at the transmitter and at the receiver.

8. The serial communication link of claim 1 , wherein a duration of the uniform latency is communicated from the transmitter to the receiver.

9. The serial communication link of claim 1 , wherein a duration of a period of time from the occurrence of the transmitter-side event to the assertion of the receiver-side event corresponds to the uniform latency.

10. The serial communication link of claim 1 , wherein the assertion of the receiver-side event occurs a duration of the uniform latency after the occurrence of the transmitter-side event.

11. A serial communication link, comprising:

a transmitter and a receiver configured to define a uniform latency between a transmitter-side event and a receiver-side event;

the transmitter comprising:

delay circuitry configured to receive the transmitter-side event and delay the transmitter-side event by a delay time corresponding to a frame time; and

control circuitry configured to prevent additional frames from being started while the transmitter-side event is being delayed; and

transmission circuitry configured to send an event frame corresponding to the transmitter-side event after the delay time, wherein the transmission circuitry is configured to include, in the event frame: event identifier bits indicative that the frame being transmitted is an event frame and one or more error bits indicating whether the event indicator was delayed for a period of time longer than the frame time; and

the receiver comprising:

receive circuitry configured to:

decode the frame being transmitted as the event frame; and

assert the receiver-side event responsive to the decoding.

12. A method of communicating on a serial communication link, comprising:

obtaining, at a transmitter, a transmitter-side event at a first time;

delaying, at the transmitter, the transmitter-side event for a delay time, the duration of the delay time corresponding to a frame length;

preventing, at the transmitter, additional frames from being transmitted during the delay time;

transmitting an event frame corresponding to the transmitter-side event after the delay time, the event frame including event-identifier bits indicative that the event frame is an event frame;

receiving, at a receiver, the event frame; and

asserting, at the receiver, a receiver-side event at a second time, the second time being a fixed delay time after the first time.

13. The method of claim 12 , further comprising:

obtaining, at the transmitter, a second transmitter-side event at a third time;

delaying, at the transmitter, the second transmitter-side event for a second delay time, the duration of the second delay time corresponding to the frame length;

preventing, at the transmitter, additional frames from being transmitted during the second delay time;

transmitting a second event frame corresponding to the second transmitter-side event after the second delay time, the second event frame including second event-identifier bits indicative that the second event frame is an event frame;

receiving, at the receiver, the second event frame; and

asserting, at the receiver, a second receiver-side event at a fourth time, the fourth time being the fixed delay time after the third time.

Assignments (14)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 16, 2025
From: MICROCHIP TECHNOLOGY INC.; MICROCHIP TECHNOLOGY IRELAND LIMITED; MICROSEMI CORPORATION; ATMEL CORPORATION; SILICON STORAGE TECHNOLOGY, INC.; MICROSEMI FREQUENCY AND TIME CORP.; MICROSEMI SEMICONDUCTOR ULC; MICROCHIP TECHNOLOGY GERMANY GMBH
To: CRESTONE IP MANAGEMENT, LLC
Reel/Frame 071991/0419 →
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0335 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059263/0001 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 058214/0625 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 052856/0909 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 4, 2018
From: LUND, MORTEN WERNER; CLARK, LLOYD; REITAN, ODD MAGNE
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 045714/0684 →