Lateral transistors and methods with low-voltage-drop shunt to body diode
Methods and systems for power semiconductor devices integrating multiple quasi-vertical transistors on a single chip. Multiple power transistors (or active regions) are paralleled, but one transistor has a lower threshold voltage. This reduces the voltage drop when the transistor is forward-biased. In an alternative embodiment, the power device with lower threshold voltage is simply connected as a depletion diode, to thereby shunt the body diodes of the active transistors, without affecting turn-on and ON-state behavior.
1. A power semiconductor device, comprising:
a first and second group of laterally-gated transistors integrated on a single semiconductor die, each said laterally-gated transistor having a first-conductivity-type source region, and a gate electrode which is capacitively coupled to a body region to selectably form a lateral channel therein, and a vertically-extended conduction region connecting a drain region to a drain extension region which is adjacent to said lateral channel;
wherein the threshold voltages of said first group of laterally-gated transistors are lower than the threshold voltages of said second group of laterally-gated transistors;
wherein the vertically-extended conduction region of at least each said second laterally-gated transistor is provided by fixed electrostatic charges in the walls of a trenched field plate, which invert a portion of said body region; and
shielding shapes interposed between the gate electrodes of said laterally-gated transistors.
2. The device of claim 1 , wherein said first conductivity type is N type.
3. The device of claim 1 , wherein said semiconductor die is made of silicon.
4. A power semiconductor device, comprising:
a first and a second laterally-gated transistor both having a portion of a first-conductivity-type source region, a gate electrode which is capacitively coupled to a body region to selectably form a lateral channel therein, a first-conductivity-type drain extension region connecting said lateral channel to a common drain electrode, and a vertically-extended source extension region connecting said source region to a common source electrode on the backside of the device;
wherein both said gate electrodes are electrically separate portions of a single thin film layer;
wherein the threshold voltage of said first laterally-gated transistor is less than the threshold voltage of said second laterally-gated transistor;
wherein the gate electrode of said first laterally-gated transistor, but not the gate electrode of said second laterally-gated transistor, is connected to said common source electrode; and
wherein said vertically-extended source extension regions are a single common region which laterally separates said first and second laterally-gated transistors.
5. A power semiconductor device, comprising:
a first and a second laterally-gated transistor both having a portion of a first-conductivity-type source region, a gate electrode which is capacitively coupled to a body region to selectably form a lateral channel therein, a first-conductivity-type drain extension region connecting said lateral channel to a common drain electrode, and a vertically-extended source extension region connecting said source region to a common source electrode on the backside of the device;
wherein both said gate electrodes are electrically separate portions of a single thin film layer;
wherein the threshold voltage of said first laterally-gated transistor is less than the threshold voltage of said second laterally-gated transistor;
wherein the gate electrode of said first laterally-gated transistor, but not the gate electrode of said second laterally-gated transistor, is connected to said common source electrode.
6. The device of claim 5 , wherein the lateral channel of said first laterally-gated transistor has a shorter lateral extent than does the lateral channel of said second laterally-gated transistor.
7. The device of claim 5 , further comprising impurities implanted in the lateral channel of said first laterally-gated transistor which decrease the threshold voltage of said first laterally-gated transistor.
8. The device of claim 5 , wherein said laterally-gated transistors both have a first-conductivity-type lateral source extension region laterally connecting said source region to said lateral channel.
9. The device of claim 5 , further comprising a shielding shape interposed between said gate electrodes.
10. The device of claim 5 , wherein said first conductivity type is N type.