Electrode pad structure of a light emitting diode
Provided is a light emitting diode (LED) mounted on a carrier substrate and including a semiconductor epitaxial structure and at least one electrode pad structure. The semiconductor epitaxial structure is electrically connected to the carrier substrate. The electrode pad structure includes a eutectic layer, a barrier layer and a ductility layer. The eutectic layer is adapted for eutectic bonding to the carrier substrate. The barrier layer is between the eutectic layer and the semiconductor epitaxial structure. The barrier layer blocks the diffusion of the material of the eutectic layer in the eutectic bonding process. The ductility layer is between the eutectic layer and the semiconductor epitaxial structure. The ductility layer reduces the stress on the LED produced by thermal expansion and contraction of the substrate during the eutectic bonding process, so as to prevent the electrode pad structure from cracking, and maintain the quality of the LED.
1. A light emitting diode, configured to be mounted to a connecting element of an external carrier substrate, the light emitting diode comprising:
a semiconductor epitaxial structure comprising a first semiconductor layer, a second semiconductor layer and a light emitting layer disposed therebetween, wherein a portion of the first semiconductor layer is exposed by the second semiconductor layer and the light emitting layer;
a current blocking layer disposed on the second semiconductor layer;
a current dispersing layer covering the current blocking layer and in contact with the second semiconductor layer;
a first metal layer disposed on the exposed first semiconductor layer;
a second metal layer disposed on the current dispersing layer and aligned with the current blocking layer;
a distributed Bragg reflector (DBR) layer disposed over the semiconductor epitaxial structure, wherein the DBR layer comprises at least one first opening to expose the first metal layer and a plurality of second openings to expose the second metal layer;
a first electrode pad structure disposed on a top surface of the DBR layer and filled into the at least one first opening; and
a second electrode pad structure disposed on the top surface of the DBR layer and filled into the second openings, wherein at least one of the first electrode pad structure and the second electrode pad structure comprises:
a ductility layer, comprising gold and disposed upon the top surface of the DBR layer and filled into one of the at least one first opening and the second openings;
a eutectic layer for soldering with the connecting element of the external carrier substrate, the eutectic layer being disposed on the ductility layer; and
a barrier layer for blocking diffusion of material of the eutectic layer, disposed between the ductility layer and the eutectic layer,
wherein the eutectic layer is disposed within a region of the ductility layer, and a total area of the eutectic layer is less than a total area of the ductility layer.
2. The light emitting diode of claim 1 , wherein the eutectic layer comprises at least one material selected from the group consisting of Au, Au/Sn and Sn/Ag/Cu.
3. The light emitting diode of claim 1 , wherein the barrier layer comprises at least one material selected from the group consisting of Ni, Ti and Pt.
4. The light emitting diode of claim 1 , wherein the ductility layer further comprises at least one material selected from the group consisting of Al, Ni, Ti, Cr and Pt.
5. The light emitting diode of claim 1 , further comprising an adhesive layer disposed between the ductility layer and one of the first metal layer and the second metal layer.
6. The light emitting diode of claim 1 , wherein the eutectic layer is divided into a plurality of blocks separately disposed on the ductility layer.
7. A light emitting diode, configured to be mounted to a connecting element of an external carrier substrate, the light emitting diode comprising:
a semiconductor epitaxial structure;
an insulating layer disposed over the semiconductor epitaxial structure, wherein the insulating layer comprises at least one opening to expose the semiconductor epitaxial structure; and
at least one electrode pad structure disposed on a top surface of the insulating layer and filled into the at least one opening, wherein the semiconductor epitaxial structure is electrically connected to the at least one electrode pad structure, and the at least one electrode pad structure comprises:
a ductility layer, comprising gold and disposed upon the top surface of the insulating layer and filled into the at least one opening;
a eutectic layer for soldering with the connecting element of the external carrier substrate, the eutectic layer being disposed on the ductility layer; and
a barrier layer for blocking diffusion of material of the eutectic layer, disposed between the ductility layer and the eutectic layer,
wherein the eutectic layer is disposed within a region of the ductility layer, and a total area of the eutectic layer is less than a total area of the ductility layer.
8. The light emitting diode of claim 7 , wherein the eutectic layer comprises at least one material selected from the group consisting of Au, Au/Sn and Sn/Ag/Cu.
9. The light emitting diode of claim 7 , wherein the barrier layer comprises at least one material selected from the group consisting of Ni, Ti and Pt.
10. The light emitting diode of claim 7 , wherein the ductility layer further comprises at least one material selected from the group consisting of Al, Ni, Ti, Cr and Pt.
11. The light emitting diode of claim 7 , further comprising an adhesive layer disposed between the ductility layer and the semiconductor epitaxial structure.
12. The light emitting diode of claim 11 , wherein the adhesive layer comprises at least one material selected from the group consisting of Ni, Ti, Cr and Pt.
13. The light emitting diode of claim 7 , wherein the at least one electrode pad structure comprises a first electrode pad structure and a second electrode pad structure separated from each other.
14. The light emitting diode of claim 7 , wherein the eutectic layer is divided into a plurality of blocks separately disposed on the ductility layer.
15. A light emitting diode, configured to be mounted to a connecting element of an external carrier substrate, the light emitting diode comprising:
a semiconductor epitaxial structure;
an insulating layer disposed over the semiconductor epitaxial structure, wherein the insulating layer comprises at least one opening to expose the semiconductor epitaxial structure; and
at least one electrode pad structure disposed on a top surface of the insulating layer and filled into the at least one opening, wherein the semiconductor epitaxial structure is electrically connected to the at least one electrode pad structure, and the at least one electrode pad structure comprises:
a ductility layer, comprising gold and disposed upon the top surface of the insulating layer and filled into the at least one opening; and
a eutectic layer for soldering with the connecting element of the external carrier substrate, the eutectic layer being disposed on the ductility layer;
wherein the eutectic layer is disposed within a region of the ductility layer and a material of the ductility layer is different from a material of the eutectic layer,
wherein a total area of the eutectic layer is less than a total area of the ductility layer.
16. The light emitting diode of claim 15 , wherein the eutectic layer comprises at least one material selected from the group consisting of Au, Au/Sn and Sn/Ag/Cu.
17. The light emitting diode of claim 15 , wherein the ductility layer comprises at least one material selected from the group consisting of Al, Ni, Ti, Cr and Pt.
18. The light emitting diode of claim 15 , further comprising an adhesive layer formed between the ductility layer and the semiconductor epitaxial structure.
19. The light emitting diode of claim 18 , wherein the adhesive layer comprises at least one material selected from the group consisting of Ni, Ti, Cr and Pt.
20. The light emitting diode of claim 15 , wherein the eutectic layer is divided into a plurality of blocks separately disposed on the ductility layer.