Floating gate spacer for controlling a source region formation in a memory cell
A method is provided for forming an integrated circuit memory cell, e.g., flash memory cell. A pair of spaced-apart floating gate structures may be formed over a substrate. A non-conformal spacer layer may be formed over the structure, and may include spacer sidewall regions laterally adjacent the floating gate sidewalls. A source implant may be performed, e.g., via HVII, to define a source implant region in the substrate. The spacer sidewall region substantially prevents penetration of source implant material, such that the source implant region is self-aligned by the spacer sidewall region. The source implant material diffuses laterally to extend partially under the floating gate. Using the non-conformal spacer layer, including the spacer sidewall regions, may (a) protect the upper corner, or “tip” of the floating gate from rounding and (b) provide lateral control of the source junction edge location under each floating gate.
1. A method of forming a memory cell of a semiconductor device, the method comprising:
forming a floating gate structure over a substrate;
forming an oxide region over the floating gate structure, wherein the formation of the oxide region forms an upwardly-pointing floating gate tip region of the floating gate structure;
forming a non-conformal spacer layer including a spacer sidewall region laterally adjacent a sidewall of the floating gate and extending over and covering the upwardly-pointing floating gate tip region such that a vertical plane passes through the spacer sidewall region and the floating late tip region; and
performing a source implant into the substrate, wherein the spacer sidewall region laterally adjacent the sidewall of the floating gate and extending over and covering the upwardly-pointing floating gate tip region substantially prevents a vertical penetration of source implant material through the spacer sidewall region, to thereby (a) protect the upwardly-pointing floating gate tip region from receiving the source implant material and (b) define a self-aligned source implant region in the substrate.
2. The method of claim 1 , wherein forming a non-conformal spacer layer comprises:
depositing a first spacer layer over the floating gate structure and over a region of the substrate laterally adjacent the floating gate structure; and
etching the first spacer layer.
3. The method of claim 2 , wherein etching the first spacer layer:
(a) defines the spacer sidewall region laterally adjacent the sidewall of the floating gate structure, and
(b) removes a full thickness of the first spacer layer over an area of the substrate laterally the adjacent spacer sidewall region.
4. The method of claim 2 , wherein etching the first spacer layer:
(a) defines the spacer sidewall region laterally adjacent the sidewall of the floating gate structure, and
(b) partially removes a thickness of the first spacer layer over an area of the substrate laterally the adjacent spacer sidewall region to define a reduced-thickness spacer layer area laterally adjacent the spacer sidewall region.
5. The method of claim 2 , wherein the deposited first spacer layer has a thickness of at least 1000 Å, or at least 1500 Å, or between 1000-2000 Å, or between 1300-1800 Å, or between 1500-1600 Å.
6. The method of claim 2 , wherein the spacer sidewall region defined by the etch has a lateral width at a bottom of the spacer sidewall region of between 500-1500 Å, or between 700-1300 Å, or between 800-1000 Å.
7. The method of claim 2 , wherein
the first spacer layer is deposited with a spacer layer thickness; and
the spacer sidewall region defined by the etch has a lateral width, at a bottom of the spacer sidewall region, that is less than the spacer layer thickness, or less than 80% of the spacer layer thickness, or less than 65% of the spacer layer thickness, or less than 50% of the spacer layer thickness, or between 25%-80% of the spacer layer thickness, or between 40%-65% of the spacer layer thickness.
8. The method of claim 1 , wherein the source implant material implanted into the substrate diffuses laterally underneath a portion of the floating gate structure.
9. The method of claim 1 , wherein the non-conformal spacer layer comprises nitride.
10. The method of claim 1 , comprising:
forming first and second floating gate structures over the substrate;
forming a first oxide region over the first floating gate structure and a second oxide region over the second floating gate structure, wherein the formation of the first and second oxide regions forms a first upwardly-pointing floating gate tip region of the first floating gate structure and a second upwardly-pointing floating gate tip region of the second floating gate structure;
wherein the non-conformal spacer layer includes:
a first spacer sidewall region laterally adjacent a first sidewall of the first floating gate facing the second floating gate and extending over and covering the first upwardly-pointing floating gate tip region such that a first vertical plane passes through the spacer sidewall region and the floating gate tip region; and
a second spacer sidewall region laterally adjacent a second sidewall of the second floating gate facing the first floating gate and extending over and covering the second upwardly-pointing floating gate tip region such that a second vertical plane passes through the spacer sidewall region and the floating gate tip region; and
performing a source implant into the substrate, wherein the first and second spacer sidewall regions substantially prevent a vertical penetration of source implant material through the first and second spacer sidewall regions, to thereby (a) protect the first and second upwardly-pointing floating gate tip regions from receiving the source implant material and (b) define a self-aligned source implant region in the substrate laterally between the first and second floating gates.
11. The method of claim 1 , wherein the memory cell comprises a flash memory cell.
12. The method of claim 1 , wherein the memory cell comprises a mirrored flash memory cell.
13. The method of claim 1 , further comprising forming an erase gate adjacent the floating gate structure and overlapping the upwardly-pointing floating gate tip region.
14. The method of claim 1 , further comprising forming a shared erase gate between the between the first and second floating gate structures and overlapping the first and second upwardly-pointing floating gate tip regions.
15. A method of forming a memory cell of a semiconductor device, the method comprising:
forming a floating gate structure over a substrate;
forming a non-conformal spacer layer by:
depositing a first material to form a continuous first spacer layer over the floating gate structure and over a region of the substrate laterally adjacent the floating gate structure; and
etching the first spacer layer formed of the first material to:
(a) define a spacer sidewall region of the first material laterally adjacent a sidewall of the floating gate structure and covering a portion of the floating gate structure such that a vertical plane passes through the spacer sidewall region and the floating gate structure, and
(b) partially remove a thickness of the first material over an area of the substrate laterally the adjacent spacer sidewall region to define a reduced-thickness spacer layer area laterally adjacent the spacer sidewall region; and
performing a source implant into the substrate, wherein the spacer sidewall region substantially prevents a vertical penetration of source implant material through the spacer sidewall region, to thereby define a self-aligned source implant region in the substrate.
16. A method of forming a memory cell of a semiconductor device, the method comprising:
forming first and second floating gate structures over a substrate;
forming a first oxide region over the first floating gate structure and a second oxide region over the second floating gate structure, wherein the formation of the first and second oxide regions forms a first upwardly-pointing floating gate tip region of the first floating gate structure and a second upwardly-pointing floating gate tip region of the second floating gate structure;
forming a non-conformal spacer layer including:
a first spacer sidewall region laterally adjacent a first sidewall of the first floating gate structure facing the second floating gate and extending over and covering the first upwardly-pointing floating gate tip region such that a first vertical plane passes through the spacer sidewall region and the floating gate tip region; and
a second spacer sidewall region laterally adjacent a second sidewall of the second floating gate structure facing the first floating gate and extending over and covering the second upwardly-pointing floating gate tip region such that a second vertical plane passes through the spacer sidewall region and the floating gate tip region; and
performing a source implant into the substrate, wherein the first and second spacer sidewall regions substantially prevent a vertical penetration of source implant material through the first and second spacer sidewall regions, to thereby (a) protect the first and second upwardly-pointing floating gate tip regions from receiving the source implant material and (b) define a self-aligned source implant region in the substrate laterally between the first and second floating gate structures.