Low-voltage crystal oscillator circuit compatible with GPIO
Low voltage crystal oscillator having native NMOS transistors used for coupling/decoupling to/from GPIO. The native NMOS transistors function properly at a low supply voltage when on (low resistance) and a high supply voltage when off (high resistance). Oscillator Gm driver bias resistors are repurposed to degenerate the native NMOS transistors when they are off, thereby reducing the leakage current thereof (oscillator circuit decoupled from GPIO nodes). This ensures compliance with the CMOS IIH leakage current specification during an external clock (EC) mode at a high supply voltage.
1. A crystal oscillator circuit having low leakage current isolation, comprising:
an NMOS Gm-driver transistor;
a constant current source coupled between a voltage source and a drain of the NMOS Gm-driver transistor;
first and second Gm driver bias resistors coupled in series between the drain and a gate of the NMOS Gm-driver transistor;
a current leakage reduction transistor coupled between a junction of the first and second Gm driver bias resistors and a voltage source common;
first and second connection nodes adapted for coupling to a frequency determining crystal;
a first isolation transistor coupled between the first connection node and the gate of the current leakage reduction transistor;
a second isolation transistor coupled between the second connection node and the drain of the NMOS Gm-driver transistor;
wherein
when the first and second isolation transistors are turned on the gate and drain of the NMOS Gm-driver transistor are coupled to the first and second connection nodes, respectively, and the current leakage reduction transistor is turned off, and
when the first and second isolation transistors are turned off the gate and drain of the NMOS Gm-driver transistor are decoupled from the first and second connection nodes, respectively, and the current leakage reduction transistor is turned on which couples the junction of the first and second Gm driver bias resistors to the voltage source common whereby the first and second isolation transistors self-limit current therethrough.
2. The crystal oscillator circuit according to claim 1 , wherein the Gm-driver transistor is a N-channel metal oxide semiconductor field effect transistor (NMOS FET).
3. The crystal oscillator circuit according to claim 1 , wherein the current leakage reduction transistor is a N-channel metal oxide semiconductor field effect transistor (NMOS FET).
4. The crystal oscillator circuit according to claim 1 , wherein the first and second isolation transistors are N-channel metal oxide semiconductor field effect transistors (NMOS FETs).
5. The crystal oscillator circuit according to claim 4 , wherein the first and second isolation transistors are low-threshold voltage native NMOS FETs.
6. The crystal oscillator circuit according to claim 1 , wherein a combined series resistance of the first and second Gm driver bias resistors is about seven (7) megohms.
7. The crystal oscillator circuit according to claim 1 , wherein a combined series resistance of the first and second Gm driver bias resistors is from about five (5) megohms to about ten (10) megohms.
8. The crystal oscillator circuit according to claim 1 , further comprising a clock buffer having inputs coupled to the NMOS Gm-driver transistor and a clock output.
9. The crystal oscillator circuit according to claim 1 , wherein when the first and second isolation transistors are turned off their leakage current meets a complementary metal oxide semiconductor (CMOS) input-leakage high (IIH) specification for shared general-purpose input-output (GPIO) nodes.
10. The crystal oscillator circuit according to claim 1 , wherein the first and second connection nodes are adapted to be first and second general purpose input output (GPIO) nodes, respectively.
11. A microprocessor, comprising:
a central processing unit (CPU) and memory;
a crystal oscillator circuit having low leakage current isolation, comprising
an NMOS Gm-driver transistor;
a constant current source coupled between a voltage source and a drain of the NMOS Gm-driver transistor;
first and second Gm driver bias resistors coupled in series between the drain and a gate of the NMOS Gm-driver transistor;
a current leakage reduction transistor coupled between a junction of the first and second Gm driver bias resistors and a voltage source common;
first and second connection nodes adapted for coupling to a frequency determining crystal;
a first isolation transistor coupled between the first connection node and the gate of the NMOS Gm-driver transistor;
a second isolation transistor coupled between the second connection node and the drain of the NMOS Gm-driver transistor;
wherein
when the first and second isolation transistors are turned on the gate and drain of the NMOS Gm-driver transistor are coupled to the first and second connection nodes, respectively, and the current leakage reduction transistor is turned off, and
when the first and second isolation transistors are turned off the gate and drain of the NMOS Gm-driver transistor are decoupled from the first and second connection nodes, respectively, and the current leakage reduction transistor is turned on which couples the junction of the first and second Gm driver bias resistors to the voltage source common whereby the first and second isolation transistors self-limit current therethrough; and
at least one function module, wherein the at least one function module is coupled to the first and second connection nodes through isolation switches, whereby the oscillator circuit or the at least one function module uses the first and second connection nodes for coupling thereto.
12. The microprocessor according to claim 11 , wherein the at least one function module is an analog function module.
13. The microprocessor according to claim 11 , wherein the at least one function module is a digital function module.
14. The microprocessor according to claim 11 , further comprising an integrated circuit package and having the first and second connection nodes adapted as external connections on the integrated circuit package.
15. The microprocessor according to claim 14 , further comprising a frequency determining crystal coupled to the external connections on the integrated circuit package.
16. A method of coupling and decoupling a crystal oscillator with low resistance on and high resistance off isolation switches, said method comprising the steps of:
providing a crystal oscillator comprising
an NMOS Gm-driver transistor;
first and second Gm driver bias resistors coupled in series between the drain and a gate of the NMOS Gm-driver transistor; and
a constant current source coupled between a voltage source and a drain of the NMOS Gm-driver transistor;
providing an isolation circuit comprising
a current leakage reduction transistor coupled between a junction of the first and second Gm driver bias resistors and a voltage source common;
first and second connection nodes adapted for coupling to a frequency determining crystal;
a first isolation transistor coupled between the first connection node and the gate of the NMOS Gm-driver transistor;
a second isolation transistor coupled between the second connection node and the drain of the NMOS Gm-driver transistor;
coupling the gate and drain of the NMOS Gm-driver transistor to the first and second connection nodes, respectively, when the first and second isolation transistors are turned on and the current leakage reduction transistor is turned off; and
decoupling the gate and drain of the NMOS Gm-driver transistor from the first and second connection nodes, respectively, when the first and second isolation transistors are turned off and the current leakage reduction transistor is turned on.
17. The method according to claim 16 , further comprising the step of current self-limiting the first and second isolation transistors when the current leakage reduction transistor is turned on.
18. The method according to claim 16 , further comprising the step of buffering an output of the Gm-driver transistor with a clock buffer.
19. The method according to claim 16 , further comprising the step of coupling the first and second connection nodes to first and second general purpose input-output (GPIO) nodes, respectively.
20. The method according to claim 19 , further comprising the step of providing an integrated circuit package having external connections thereon as the first and second general purpose input-output (GPIO) nodes.