Structure and method for FinFET device with contact over dielectric gate

1. A semiconductor structure, comprising:

a first fin active region and a second fin active region extruded from a semiconductor substrate;

an isolation feature formed in the semiconductor substrate and being interposed between the first and second fin active regions;

a dielectric gate directly disposed on the isolation feature, wherein the dielectric gate is a dielectric feature different from the isolation feature in composition;

a first gate stack disposed on the first fin active region and a second gate stack disposed on the second fin active region;

a first source/drain feature formed in the first fin active region and interposed between the first gate stack and the dielectric gate;

a second source/drain feature formed in the second fin active region and interposed between the second gate stack and the dielectric gate; and

a contact feature formed in a first inter-level dielectric (ILD) layer and landing on the first and second source/drain features and extending over the dielectric gate.

2. The semiconductor structure of claim 1 , further comprising an interconnection structure that further includes a first metal layer with multiple metal lines disposed on the contact feature and coupled to the contact feature.

3. The semiconductor structure of claim 1 , wherein

each of the first and second gate stacks includes a gate dielectric layer, and a gate electrode on the gate dielectric layer.

4. The semiconductor structure of claim 3 , wherein

the gate dielectric layer includes a high k dielectric material;

the dielectric gate includes a first dielectric material;

the isolation feature includes a second dielectric material; and

the first and second dielectric materials are different from the high k dielectric material in composition.

5. The semiconductor structure of claim 4 , wherein the first dielectric material includes silicon nitride and the second dielectric material includes silicon oxide.

6. The semiconductor structure of claim 1 , wherein the isolation feature is a shallow-trench isolation (STI) feature formed on the semiconductor substrate with a top surface below top surfaces of the first and second fin active regions.

7. The semiconductor structure of claim 1 , wherein the contact feature includes a first conductive feature landing on the first source/drain feature, a second conductive feature landing on the second source/drain feature, and a third conductive feature extending from the first conductive feature to the second conductive feature.

8. The semiconductor structure of claim 7 , wherein

the first and second conductive features further include a first metal layer, and a first barrier layer on sidewalls and a bottom surface of the first metal layer; and

the third conductive feature metal further includes a second metal layer, and a second barrier layer on sidewalls and a bottom surface of the second metal layer.

9. The semiconductor structure of claim 7 , wherein the third conductive feature has a top surface being coplanar with the surfaces of the first and second conductive features.

10. The semiconductor structure of claim 1 , further comprising

a third source/drain feature on the first fin active region;

a first channel on the first fin active region and underlying the first gate stack;

a fourth source/drain feature on the second fin active region; and

a second channel on the second fin active region and underlying the second gate stack, wherein

the first and third source/drain features, the first gate stack and the first channel are components of a first field-effect transistor (FET), and

the second and fourth source/drain features, the second gate stack and the second channel are components of a second FET.

11. A semiconductor structure, comprising:

a first fin active region and a second fin active region extruded from a semiconductor substrate;

an isolation feature formed in the semiconductor substrate and being interposed between the first and second fin active regions;

a dielectric gate directly disposed on the isolation feature, the dielectric gate is a dielectric feature different from the isolation feature in composition;

a first gate stack disposed on the first fin active region and a second gate stack disposed on the second fin active region;

a first source/drain feature formed in the first fin active region and interposed between the first gate stack and the dielectric gate;

a second source/drain feature formed in the second fin active region and interposed between the second gate stack and the dielectric gate; and

a contact feature formed in a first inter-level dielectric (ILD) layer, landing on the first and second source/drain features, extending over and contacting the dielectric gate.

12. The semiconductor structure of claim 11 , further comprising an interconnection structure that further includes a first metal layer with multiple metal lines disposed on the contact feature and electrically coupled to the contact feature, wherein

the contact feature includes a first conductive feature landing on the first source/drain feature, a second conductive feature landing on the second source/drain feature, and a third conductive feature extending from the first conductive feature to the second conductive feature;

the first and second conductive features further include a first metal layer, and a first barrier layer disposed on sidewalls and a bottom surface of the first metal layer;

the third conductive feature further includes a second metal layer, and a second barrier layer disposed on sidewalls and a bottom surface of the second metal layer; and

the third conductive feature has a top surface being coplanar with the surfaces of the first and second conductive features.

13. The semiconductor structure of claim 11 , wherein each of the first and second gate stacks includes a gate dielectric layer, and a gate electrode disposed on the gate dielectric layer; and

wherein the isolation feature is a shallow-trench isolation (STI) feature formed on the semiconductor substrate with a top surface below top surfaces of the first and second fin active regions.

14. The semiconductor structure of claim 13 , wherein

the gate dielectric layer includes one of a metal oxide and a metal nitride;

the dielectric gate includes silicon nitride; and

the isolation feature includes silicon oxide.

15. A device comprising:

a first fin and a second fin disposed over a substrate;

an isolation feature disposed on the substrate and extending from the first fin to the second fin;

a dielectric gate disposed directly on the isolation feature, wherein the dielectric gate is formed of a different material than the isolation feature;

a first gate stack disposed on the first fin;

a first source/drain feature disposed in the first fin and interposed between the first gate stack and the dielectric gate; and

a contact feature extending through a first inter-level dielectric layer to the dielectric gate.

16. The device of claim 15 , wherein the isolation feature has a top surface below a top surface of the first fin.

17. The device of claim 15 , wherein the dielectric gate has a top surface above the top surface of the first fin, and

wherein the dielectric gate has a bottom surface below the top surface of the first fin.

18. The device of claim 15 , further comprising a dielectric sidewall spacer disposed along and physically contacting a sidewall surface of the dielectric gate, and

wherein the first fin physically contacts the sidewall surface of the dielectric gate.

19. The device of claim 15 , wherein the dielectric gate includes silicon nitride, and

wherein the isolation feature includes silicon oxide.

20. The device of claim 15 , further comprising:

a second gate stack disposed on the second fin; and

a second source/drain feature disposed in the second fin and interposed between the second gate stack and the dielectric gate, and

wherein the contact feature includes a first conductive feature extending from the first source/drain feature, a second conductive feature extending from the second source/drain feature, and a third conductive feature extending from the first conductive feature to the second conductive feature, and wherein the first, second and third conductive features each have a top surface such that top surfaces of the first, second and third conductive features are coplanar.