IP Library › Granted Patent US 12,432,962
Granted Patent B2
US 12,432,962 · App. 18/064,785 · Granted Sep 30, 2025

FinFET device with source/drain contact extending over dielectric gate

Inventors: Fang Chen (Hsinchu, TW); Jhon Jhy Liaw (Hsinchu County, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
H10D30/62H01L21/3212H01L21/76224H01L21/76816H01L21/7684H01L21/76843H01L21/76852H01L21/76895H01L23/5221H01L23/5226H01L23/528H01L23/5283H10D30/024H10D30/6211H10D30/6219H10D62/83H10D64/01H10D64/017H10D64/021H10D64/62H10D84/0149H10D84/0151H10D84/0158H10D84/0186H10D84/0188H10D84/038H10D84/834H10D84/853H01L21/31053H01L21/31111H01L21/76819H01L21/76871H01L23/53214H01L23/53223H01L23/53238H01L23/53266H10D30/0212H10D30/797H10D62/021H10D62/822H10D64/514H10D64/667H10D64/685H10D64/691H10D64/693
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Quick Facts
Patent No.
US 12,432,962
App. No.
18/064,785
Granted
Sep 30, 2025
Kind
B2
Abstract

The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a first active region and a second fin active region extruded from a semiconductor substrate; an isolation featured formed in the semiconductor substrate and being interposed between the first and second fin active regions; a dielectric gate disposed on the isolation feature; a first gate stack disposed on the first fin active region and a second gate stack disposed on the second fin active region; a first source/drain feature formed in the first fin active region and interposed between the first gate stack and the dielectric gate; a second source/drain feature formed in the second fin active region and interposed between the second gate stack and the dielectric gate; a contact feature formed in a first inter-level dielectric material layer and landing on the first and second source/drain features and extending over the dielectric gate.

Claims (44)

1. A device comprising:

a first fin feature disposed on a substrate;

a dielectric isolation feature disposed on the substrate;

a first dielectric gate disposed on and interfacing with a first portion of the dielectric isolation feature, wherein the first dielectric gate is formed of a different material than the dielectric isolation feature;

a second dielectric gate interfacing with a second portion of the dielectric isolation feature, the first dielectric gate extending to a first height over the substrate and the second dielectric gate extending to a second height over the substrate, the second height being different than the first height;

a first source/drain feature disposed on the first fin feature; and

a contact feature extending from the first dielectric gate to the first source/drain feature.

2. The device of claim 1 , wherein the second height is greater than the first height.

3. The device of claim 1 , wherein the second dielectric gate interfaces with the first fin feature.

4. The device of claim 1 , further comprising a second fin feature disposed on the substrate, and

wherein the first portion of the dielectric isolation feature interfaces with the first fin feature and the second fin feature.

5. The device of claim 4 , wherein the first dielectric gate interfaces with the first fin feature and the second fin feature.

6. The device of claim 1 , wherein the first dielectric gate includes a nitride material and the dielectric isolation feature includes an oxide material.

7. The device of claim 1 , a first gate stack disposed on the first fin feature, the first gate stack formed of a different material than the first dielectric gate.

8. The device of claim 7 , wherein the first gate stack and the second dielectric gate extend to the same second height over the substrate.

9. A device comprising:

a first active region and a second active region disposed on a substrate;

a dielectric isolation feature disposed on the substrate, the dielectric isolation feature interfacing with the first active region and the second active region;

a first dielectric structure interfacing with the dielectric isolation feature, wherein the first dielectric structure is a dielectric feature different from the dielectric isolation feature in composition;

a first source/drain feature disposed on the first active region;

a metal gate structure disposed on the first active region and adjacent the first source/drain feature;

a second source/drain feature disposed on the second active region; and

a contact feature extending continuously from the first source/drain feature to the second source/drain feature such that the contact feature interfaces with the first source/drain feature, the first dielectric structure and the second source/drain feature,

wherein the first dielectric structure interfaces sidewalls of the first active region and the second active region.

10. The device of claim 9 , wherein the first source/drain feature extends within the first active region to a first depth, and

wherein the first dielectric structure extends towards the substrate between the first active region and the second active region to a second depth that is greater than the first depth.

11. The device of claim 9 , wherein the dielectric isolation feature is thicker than the first dielectric structure.

12. The device of claim 9 , wherein a portion of the first active region is disposed between the first source/drain feature and the first dielectric structure.

13. The device of claim 9 , further comprising a second dielectric structure disposed on at least a portion of the first active region.

14. The device of claim 13 , wherein the second dielectric structure is further disposed on at least a portion of the dielectric isolation feature.

15. The device of claim 9 , wherein a bottommost surface of the contact feature interfaces a top surface of the first dielectric structure.

16. A device comprising:

a first fin feature disposed on a substrate;

an isolation feature disposed on the substrate;

a first source/drain feature disposed on the first fin feature;

a second source/drain feature disposed on the first fin feature;

a first dielectric gate disposed directly on a first portion of the isolation feature, the first dielectric gate being formed of a different material than the isolation feature;

a second dielectric gate disposed directly on a second portion of the isolation feature and the second source/drain feature, the second dielectric gate extending to a different height above the substrate than the first dielectric gate; and

a first contact feature disposed directly on the first dielectric gate and the first source/drain feature.

17. The device of claim 16 , wherein the first portion of the isolation feature and the second portion of the isolation feature extend to the same height above the substrate.

18. The device of claim 16 , wherein the first dielectric gate includes a nitride material and the isolation feature includes an oxide material.

19. The device of claim 16 , further comprising a first gate stack disposed on the first fin feature, the first gate stack formed of a different material than the first dielectric gate, the first gate stack disposed between the first source/drain feature and the second source/drain feature.

20. The device of claim 16 , further comprising a second contact feature extending to and interfacing with the second source/drain feature, and

wherein the first contact feature is wider than the second contact feature.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2022
From: CHEN, FANG; LIAW, JHON JHY
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 062083/0244 →
Continuity (4)
Continuation 17068162 · Oct 12, 2020
Continuation 16734968 · Jan 6, 2020
Division 15993970 · May 31, 2018
Related Publication 20230115015A1 · Apr 13, 2023
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