Structure and method for FinFET device with contact over dielectric gate

1. A method comprising:

forming a first fin feature and a second fin feature over a substrate, wherein a dielectric isolation structure is disposed over the substrate and a first portion of the dielectric isolation structure extends from the first fin feature to the second fin feature;

forming a first gate stack directly on the first fin structure and forming a second gate stack directly on the first portion of the dielectric isolation structure;

removing a portion of the first gate stack to form a first trench;

forming a gate electrode layer in the first trench;

removing a portion of the second gate stack to form a second trench, wherein the first portion of the dielectric isolation structure is exposed within the second trench; and

forming a dielectric material in the second trench such that the second trench is completely filled with the dielectric material.

2. The method of claim 1 , wherein a portion of the first fin feature is exposed within the first trench after the removing of the portion of the first gate stack to form the first trench.

3. The method of claim 1 , further comprising forming a gate dielectric on the exposed portion of the first fin feature, and

wherein the forming of the gate electrode layer in the first trench includes forming the gate electrode layer on the gate dielectric.

4. The method of claim 1 , wherein the dielectric material is formed of a different composition than the dielectric isolation structure.

5. The method of claim 1 , further comprising forming a third gate stack on the second fin feature, wherein the third gate stack extend to the dielectric isolation structure disposed on the substrate.

6. The method of claim 5 , wherein the removing of the portion of the second gate stack to form the second trench includes removing a portion of the third gate stack to form a third trench, wherein a second portion of the dielectric isolation structure is exposed by the third trench, and

wherein the forming of the dielectric material in the second trench includes forming the dielectric material in third trench such that the third trench is completely filled with the dielectric material.

7. The method of claim 1 , further comprising:

forming a source/drain feature on the first fin feature;

forming a contact feature extending from the source/drain feature; and

removing a first portion of the dielectric material, wherein a second portion of the dielectric material remains after the removing of the first portion; and

forming an interconnect feature directly on the second portion of the dielectric material and the contact feature.

8. A method comprising:

forming a dielectric isolation structure over a substrate;

forming a first fin active region and a second fin active region over the substrate;

forming a first gate stack over the first fin active region and a second gate stack over a first portion of the dielectric isolation structure, the first gate stack including a first dielectric layer and a first gate electrode layer and the second gate stack includes a second dielectric layer and a second gate electrode layer;

removing the first dielectric layer and the first gate electrode layer to form a first trench, wherein a first portion of the fin active region is exposed within the first trench;

forming a third dielectric layer and a third gate electrode layer in the first trench;

removing the second dielectric layer and the second gate electrode layer to form a second trench, wherein the first portion of the dielectric isolation structure is exposed within the second trench; and

forming a dielectric material in the second trench directly on the first portion of the dielectric isolation structure such that the dielectric material completely fills the second trench.

9. The method of claim 8 , further comprising:

forming a first source/drain feature in the first fin active region and a second source/drain feature in the second fin active region;

forming an interlayer dielectric layer over the first and second source/drain features;

removing a first portion of the dielectric material and a portion of the interlayer dielectric layer to expose the first and second source/drain features; and

forming a contact on the exposed first and second source/drain features.

10. The method of claim 9 , wherein a second portion of the dielectric material remains disposed over the first portion of the dielectric isolation feature after the removing of the first portion of the dielectric material.

11. The method of claim 9 , wherein a top surface of the first fin active region and top surface of the second portion of the dielectric material are at the same level.

12. The method of claim 8 , wherein forming the second gate stack over a first portion of the dielectric isolation structure includes forming the second gate stack over the second fin active region.

13. The method of claim 12 , wherein a sidewall spacer of the second gate stack is disposed over a top surface of the second fin active region.

14. The method of claim 8 , further comprising forming a source/drain feature on the first fin active region prior to the removing of the first dielectric layer and the first gate electrode layer to form the first trench.

15. The method of claim 8 , wherein the dielectric material is formed of a different material than the dielectric isolation structure.

16. A method of forming an integrated circuit structure, the method comprising:

forming a first and a second fin active region on a semiconductor substrate, wherein the first and second fin active regions are interposed by a shallow trench isolation (STI) feature;

forming a first, a second and a third dummy gate landing on the first fin active region, the STI feature, and the second fin active region, respectively;

forming a first source/drain feature on the first fin active region between the first dummy gate and the second dummy gate, and a second source/drain feature on the second fin active region between the second dummy gate and the third dummy gate;

forming an inter-layer dielectric (ILD) layer on the semiconductor substrate;

replacing the first and third dummy gates with a first metal gate and a second metal gate, respectively;

replacing the second dummy gate with a dielectric gate;

patterning the ILD layer to form a first and a second trench to expose the first and second source/drain features, respectively;

forming a first and a second conductive feature in the first and second trenches, respectively;

forming a local interconnection feature contacting the first and second conductive features; and

forming an interconnection structure that further includes a first metal layer with multiple metal lines that are disposed above the first and conductive features and the local interconnection feature.

17. The method of claim 16 , wherein

the forming of a first, a second and a third dummy gate includes depositing a dummy gate material and patterning the dummy gate material, thereby forming the first, the second and the third dummy gates;

the replacing of the first and third dummy gates with a first metal gate and a second metal gate, respectively includes removing the first and third dummy to form a third trench and a fourth trench, filling the third and fourth trenches with a metal electrode, and performing a first chemical mechanical polishing (CMP) process; and

the replacing of the second dummy gate with a dielectric gate includes removing the second dummy gate to form a fifth trench, filling the fifth trench with a dielectric material, and performing a second CMP process.

18. The method of claim 17 , wherein the forming of a local interconnection feature contacting the first and second conductive features includes patterning the ILD layer to form a sixth trench, filling the sixth trench with a conductive material, and performing a second CMP process, causing the first and conductive features and the local interconnection feature to have a coplanar top surface.

19. The method of claim 18 , wherein the patterning the ILD to form a sixth trench includes etching the ILD layer and the dielectric gate to form the sixth trench that exposes the first and second conductive features.

20. The method of claim 15 , wherein the dielectric gate interfaces with the STI.