Interleaved program and verify in non-volatile memory
A circuit includes a program controller configured to perform a program operation with interleaved program-verify loops to program memory cells in a same block. During each program-verify loop, a control gate line voltage supply circuit first supplies a program pulse to a first cell of the block and then, before verifying the first cell, supplies a program pulse to a second cell of the block. After the program pulses are sent, the control gate line supply circuit consecutively supplies verify pulses to the first cell and the second cell such that a delay is introduced between the respective program and verify stages of the first and second cells. Additionally, a constant voltage bias on common control gate lines of the first and second memory cells is applied during the consecutive verify stages. Further, an order of verify pulses may be applied in a reverse order during a verify stage.
1. A circuit comprising:
an interleave control circuit configured to determine a sequence for interleaving two program-verify loops;
a program control circuit configured to
apply a first program pulse to a first memory cell of a block during a first program stage according to the sequence; and
apply a second program pulse to a second memory cell of the block during a second program stage, after application of the first program pulse and before application of a first plurality of verify pulses to the first memory cell of the block, according to the sequence; and
a verify control circuit configured to
apply the first plurality of verify pulses to the first memory cell of the block during a first verify stage according to the sequence; and
apply a second plurality of verify pulses to the second memory cell of the block during a second verify stage according to the sequence, after application of the first plurality of verify pulses;
wherein at least one of the first or second plurality of verify pulses, applied during at least one of the first or second verify stages, has sequentially decreasing verify pulse levels.
2. The circuit of claim 1 , wherein the first and second verify stages are consecutive verify stages.
3. The circuit of claim 2 , wherein the verify control circuit is further configured to maintain a drain select gate line voltage on a selected drain select gate line at a constant level over a duration of the first verify stage and the second verify stage.
4. The circuit of claim 1 , wherein the first and second plurality of verify pulses, applied by the voltage control circuitry during first and second verify stages, each have sequentially decreasing verify pulse levels and thereby enable the verify control circuit to check program statuses for the first and second memory cells of the block in a descending verify order during each of the first verify stage and the second verify stage.
5. The circuit of claim 2 , wherein the verify control circuit is configured to apply a plurality of verify pulse sequences in reverse verify orders during the first verify stage and the second verify stage.
6. The circuit of claim 1 , wherein the verify control circuit is configured to cause only one of the first or second plurality of verify pulses to have sequentially decreasing verify pulse levels, and cause the other one of the first or second plurality of verify pulses to have sequentially increasing verify pulse levels, to thereby enable the verify control circuit to check program statuses for one of the first or second memory cells of the block in an ascending verify order during one of the first or second verify stages, and to check program statuses for the other one of the first or second memory cells of the block in a descending verify order during the other one of the first or second verify stages.
7. The circuit of claim 2 , wherein the verify control circuit is configured to maintain a bit line voltage of all of a plurality of bit lines of the block at a selected bit line level over a duration of the first verify stage and the second verify stage.
8. The circuit of claim 1 , wherein the first memory cell and the second memory cell are coupled to different word lines of the block.
9. The circuit of claim 8 , wherein the different word lines comprise a first word line and a second word line, the program control circuit configured to apply an unselected word line voltage to the second word line during application of the first program pulse to the first word line, and apply an unselected word line voltage to the first word line during application of the second program pulse to the second word line.
10. The circuit of claim 1 , wherein the first memory cell and the second memory cell, to which program and verify pulses are applied during the interleaving two program-verify loops, are each coupled to a same word line of the block.
11. The circuit of claim 10 , wherein the first memory cell is part of a first sub-block of the block, the second memory cell is part of a second sub-block of the block, the first sub-block coupled to a first drain select gate line and the second sub-block coupled to a second drain select gate line, the program control circuit configured to apply a selected drain select gate line voltage to the first drain select gate line and an unselected drain select gate line voltage to the second drain select gate line during application of the first program pulse, and apply the selected drain select gate line voltage to the second drain select gate line and the unselected drain select gate line voltage to the first drain select gate line during application of the second program pulse.
12. An apparatus comprising:
a means for determining a sequence for interleaving two program-verify loops;
a means for applying a first program pulse to a first memory cell of a block during a first program stage according to the sequence;
a means for applying a second program pulse to a second memory cell of the block during a second program stage, after application of the first program pulse and before application of a first plurality of verify pulses to the first memory cell of the block, according to the sequence; and
a means for applying the first plurality of verify pulses to the first memory cell of the block during a first verify stage according to the sequence, after application of the second program pulse; and
a means for applying a second plurality of verify pulses to the second memory cell of the block during a second verify stage according to the sequence, after application of the first plurality of verify pulses;
wherein at least one of the first or second plurality of verify pulses, applied during at least one of the first or second verify stages, has sequentially decreasing or increasing verify pulse levels.