Three-dimensional memory device containing multilevel drain select gate isolation and methods of making the same

1. A three-dimensional memory device comprising:

an alternating stack of insulating layers and word-line-level electrically conductive layers located over a substrate;

a plurality of multi-level drain select electrodes comprising a respective vertical connection portion adjoined to a respective set of drain-select-level electrically conductive layers that are vertically spaced apart among one another and located over the alternating stack;

memory stack structures comprising a respective vertical semiconductor channel laterally surrounded by a respective memory film extending through the alternating stack, and laterally surrounded by a respective gate dielectric extending through a respective one of the plurality of multi-level drain select electrodes; and

a drain-select-level isolation structure overlying the alternating stack, laterally extending along a first horizontal direction and located between a neighboring pair of the multi-level drain select electrodes, and including a pair of sidewalls that include a respective set of concave vertical sidewall segments,

wherein each multi-level drain select electrode of the plurality of multi-level drain select electrodes contacts a sidewall of a subset of the gate dielectrics; and

wherein each vertical semiconductor channel comprises:

a word-line-level semiconductor channel portion vertically extending through each of the word-line-level electrically conductive layers; and

a drain-select-level semiconductor channel portion vertically extending through each level of the drain-select-level electrically conductive layers and electrically connected to an upper portion of the word-line-level semiconductor channel portion.

2. The three-dimensional memory device of claim 1 , further comprising:

an insulating cap layer located over the alternating stack and underlying the plurality of multi-level drain select electrodes; and

an etch stop dielectric layer comprising a material different from the insulating cap layer, overlying the insulating cap layer and underlying the plurality of multi-level drain select electrodes,

wherein the drain-select-level semiconductor channel portion vertically extends through the insulating cap layer and the etch stop dielectric layer.

3. The three-dimensional memory device of claim 1 , each vertical semiconductor channel comprises a connection channel portion contacting a top end of the word-line-level semiconductor channel portion and a bottom end of the drain-select-level semiconductor channel portion and laterally surrounded by a respective one of the memory films.

4. A three-dimensional memory device comprising:

an alternating stack of insulating layers and word-line-level electrically conductive layers located over a substrate;

a plurality of multi-level drain select electrodes comprising a respective vertical connection portion adjoined to a respective set of drain-select-level electrically conductive layers that are vertically spaced apart among one another and located over the alternating stack;

memory stack structures comprising a respective vertical semiconductor channel laterally surrounded by a respective memory film extending through the alternating stack, and laterally surrounded by a respective gate dielectric extending through a respective one of the plurality of multi-level drain select electrodes; and

a drain-select-level isolation structure overlying the alternating stack, laterally extending along a first horizontal direction and located between a neighboring pair of the multi-level drain select electrodes, and including a pair of sidewalls that include a respective set of concave vertical sidewall segments,

wherein:

each multi-level drain select electrode of the plurality of multi-level drain select electrodes contacts a sidewall of a subset of the gate dielectrics;

each of the memory stack structures is completely surrounded by a respective one of the plurality of multi-level drain select electrodes;

each multi-level drain select electrode comprises a metallic barrier layer and a metallic fill material portion; and

the metallic barrier layer contacts a subset of the gate dielectrics.

5. The three-dimensional memory device of claim 4 , wherein the metallic fill material portion contacts a non-vertical surface of the drain-select-level isolation structure, wherein the non-vertical surface adjoins a bottom edge of a first vertical surface of the drain-select-level isolation structure and adjoins a top edge of a second vertical surface of the drain-select-level isolation structure.

6. A three-dimensional memory device comprising:

an alternating stack of insulating layers and word-line-level electrically conductive layers located over a substrate;

a plurality of multi-level drain select electrodes comprising a respective vertical connection portion adjoined to a respective set of drain-select-level electrically conductive layers that are vertically spaced apart among one another and located over the alternating stack;

memory stack structures comprising a respective vertical semiconductor channel laterally surrounded by a respective memory film extending through the alternating stack, and laterally surrounded by a respective gate dielectric extending through a respective one of the plurality of multi-level drain select electrodes; and

a drain-select-level isolation structure overlying the alternating stack, laterally extending along a first horizontal direction and located between a neighboring pair of the multi-level drain select electrodes, and including a pair of sidewalls that include a respective set of concave vertical sidewall segments,

wherein each multi-level drain select electrode of the plurality of multi-level drain select electrodes contacts a sidewall of a subset of the gate dielectrics;

wherein each vertical connection portion of the plurality of multi-level drain select electrodes comprises a sidewall including concave vertical sidewall segments; and

wherein each vertical connection portion of the plurality of multi-level drain select electrodes has a greater vertical extent than a vertical distance between a horizontal plane including a topmost surface of the drain-select-level electrically conductive layers and a horizontal plane including a bottommost surface of the drain-select-level electrically conductive layers.

7. A three-dimensional memory device comprising:

an alternating stack of insulating layers and word-line-level electrically conductive layers located over a substrate;

a plurality of multi-level drain select electrodes comprising a respective vertical connection portion adjoined to a respective set of drain-select-level electrically conductive layers that are vertically spaced apart among one another and located over the alternating stack;

memory stack structures comprising a respective vertical semiconductor channel laterally surrounded by a respective memory film extending through the alternating stack, and laterally surrounded by a respective gate dielectric extending through a respective one of the plurality of multi-level drain select electrodes; and

a drain-select-level isolation structure overlying the alternating stack, laterally extending along a first horizontal direction and located between a neighboring pair of the multi-level drain select electrodes, and including a pair of sidewalls that include a respective set of concave vertical sidewall segments,

wherein:

each multi-level drain select electrode of the plurality of multi-level drain select electrodes contacts a sidewall of a subset of the gate dielectrics;

the vertical connection portions of the multi-level drain select electrodes contact first areas of sidewalls of a subset of the gate dielectrics; and

the drain-select-level electrically conductive layers contact second areas of the sidewalls of the subset of the gate dielectrics.

8. The three-dimensional memory device of claim 7 , wherein each of the vertical connection portions comprises:

a laterally alternating sequence of planar vertical inner sidewall segments and concave vertical inner sidewall segments that contact a respective gate dielectric; and

a laterally alternating sequence of planar vertical outer sidewall segments and convex vertical outer sidewall segments that contact a sidewall of the respective one of the drain-select-level isolation structures.