Source/drain structure

1. A method for semiconductor processing, the method comprising:

forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium;

implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure;

implanting a second dopant into the amorphous region containing the first dopant; and

heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.

2. The method of claim 1 , wherein heating the source/drain structure is performed by a laser anneal process using a laser beam having a dwell time in a range from about 1 nanosecond to about 1000 nanoseconds.

3. The method of claim 1 , further comprising:

after heating the source/drain structure, subjecting the crystalline region to a millisecond anneal process using a laser beam or flash lamp having a dwell time in a range from about 0.01 milliseconds to about 10 milliseconds and an annealing temperature in a range from about 500° C. to about 1200° C.

4. The method of claim 1 , further comprising:

prior to heating the source/drain structure, subjecting the source/drain structure to a rapid thermal anneal process having a duration in a range from about 1 second to about 180 seconds and an annealing temperature in a range from about 400° C. to about 800° C.

5. The method of claim 4 , further comprising:

prior to subjecting the source/drain structure to the rapid thermal anneal process, subjecting the source/drain structure to a millisecond anneal process using a laser beam or flash lamp having a dwell time in a range from about 0.01 milliseconds to about 10 milliseconds and an annealing temperature in a range from about 500° C. to about 1200° C.

6. The method of claim 1 , further comprising:

prior to heating the source/drain structure, subjecting the source/drain structure to a millisecond anneal process using a laser beam or flash lamp having a dwell time in a range from about 0.01 milliseconds to about 10 milliseconds and an annealing temperature in a range from about 500° C. to about 1200° C.

7. The method of claim 6 , further comprising:

after heating the source/drain structure, subjecting the source/drain structure to a rapid thermal anneal process having a duration of about 1 seconds to about 180 seconds and an annealing temperature in a range from about 400° C. to about 800° C.

8. The method of claim 1 , wherein the source/drain structure further includes a second region comprising germanium, a concentration of germanium in the first region being greater than a concentration of germanium in the second region.

9. The method of claim 1 , wherein the first dopant comprises gallium (Ga), germanium, silicon, or a combination thereof.

10. The method of claim 1 , wherein the second dopant is a p-type dopant.

11. A method for semiconductor processing, the method comprising:

forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region having a first germanium concentration and a second region having a second germanium concentration, the first germanium concentration being greater than the second germanium concentration;

forming a dielectric layer over the active area;

forming an opening through the dielectric layer to expose at least a portion of an upper surface of the source/drain structure;

implanting a first dopant comprising gallium or germanium into the exposed source/drain structure;

after implanting the first dopant, implanting at least a second dopant comprising a p-type dopant into the exposed source/drain structure containing the first dopant;

subjecting the implanted source/drain structure containing the first dopant and at least the second dopant to a first anneal process, the first anneal process heating the implanted source/drain structure;

forming a silicide region at the upper surface of the exposed source/drain structure; and

forming a conductive feature in the opening to the upper surface of the source/drain structure.

12. The method of claim 11 , wherein the first anneal process is a laser anneal process using a laser beam having a dwell time in a range from about 1 nanosecond to about 1000 nanoseconds.

13. The method of claim 11 , wherein the first anneal process causes the first dopant and at least the second dopant to move to the upper surface of the source/drain structure.

14. The method of claim 11 , wherein at least the second dopant comprises boron, and the first anneal process causes the implanted source/drain structure to form:

a germanium concentration profile having a surface pile up profile where a peak concentration is proximate the upper surface of the source/drain structure, and having a decreasing concentration from the peak concentration with increasing depth into the source/drain structure; and

a concentration of boron profile having a surface pile up profile where a peak concentration is proximate the upper surface of the source/drain structure.

15. The method of claim 11 , wherein the first germanium concentration is in a range equal to or greater than about 25 at. %, and the second germanium concentration is in a range equal to or less than about 25 at. %.

16. A method for semiconductor processing, the method comprising:

epitaxially growing a semiconductor region on a substrate, the semiconductor region comprising a high Ge concentration region and a low Ge concentration region;

amorphizing at least a portion of the high Ge concentration region to form an amorphous region, amorphizing comprising implanting a first type of atom into the high Ge concentration region;

implanting a dopant into the amorphous region; and

performing a first anneal process to recrystallize the amorphous region to form a recrystallized region;

performing a second anneal process to liquidize and to move germanium atoms from the low Ge concentration region towards an upper surface of the semiconductor region; and

forming a silicide region at the upper surface of the semiconductor region.

17. The method of claim 16 , further comprising performing a third anneal process, the third anneal process comprising a millisecond anneal process.

18. The method of claim 17 , wherein the third anneal process is performed after the second anneal process.

19. The method of claim 16 , wherein after the second anneal process, a germanium concentration profile has a surface pile up profile.

20. The method of claim 16 , wherein second anneal process comprises a laser anneal process using a laser beam having a dwell time in a range from about 1 nanosecond to about 1000 nanoseconds.