Three-dimensional flat NAND memory device having high mobility channels and methods of making the same
A three-dimensional memory device includes alternating stacks of insulating strips and electrically conductive strips laterally spaced apart by line trenches, and an alternating two-dimensional array of memory stack assemblies and dielectric pillar structures located in the line trenches. Each of the line trenches is filled with a respective laterally alternating sequence of memory stack assemblies and dielectric pillar structures. Each memory stack assembly includes a vertical semiconductor channel and a pair of memory film. The vertical semiconductor channel includes a semiconductor channel layer having large grains, which can be provided by a selective semiconductor growth from seed semiconductor material layers, sacrificial semiconductor material layers, or a single crystalline semiconductor material in a semiconductor substrate underlying the alternating stacks.
1. A three-dimensional memory device comprising:
alternating stacks of insulating strips and electrically conductive strips located over a substrate and laterally spaced apart among one another by line trenches laterally extending along a first horizontal direction and spaced apart among one another along a second horizontal direction; and
an alternating two-dimensional array of memory stack assemblies and dielectric pillar structures located in the line trenches,
wherein each memory stack assembly comprises a vertical semiconductor channel and a pair of memory films laterally spaced apart along the second horizontal direction;
wherein the vertical semiconductor channel comprises a single crystalline semiconductor material or a polycrystalline semiconductor material having an average grain size greater than 20 nm; and
wherein the vertical semiconductor channel comprises a first U-shaped semiconductor channel layer having a first average grain size and a pair of second U-shaped semiconductor channel layers having a second average grain size that is greater than the first average grain size and contacting the first U-shaped semiconductor channel layer.
2. The three-dimensional memory device of claim 1 , wherein:
the first U-shaped semiconductor channel layer comprises polysilicon having an average grain size less than 20 nm; and
the pair of second U-shaped semiconductor channel layers comprise polysilicon having the average grain size greater than 20 nm.
3. The three-dimensional memory device of claim 2 , wherein the vertical semiconductor channel further comprises a pair of cover semiconductor layers contacting a respective one of the pair of memory films, contacting the first U-shaped semiconductor channel layer and having a different average grain size than the pair of second U-shaped semiconductor channel layers.
4. A three-dimensional memory device comprising:
alternating stacks of insulating strips and electrically conductive strips located over a substrate and laterally spaced apart among one another by line trenches laterally extending along a first horizontal direction and spaced apart among one another along a second horizontal direction; and
an alternating two-dimensional array of memory stack assemblies and dielectric pillar structures located in the line trenches,
wherein each memory stack assembly comprises a vertical semiconductor channel and a pair of memory films laterally spaced apart along the second horizontal direction;
wherein the vertical semiconductor channel comprises a single crystalline semiconductor material or a polycrystalline semiconductor material having an average grain size greater than 20 nm; and
wherein the vertical semiconductor channel has a variable thickness that decreases with a lateral distance along the first horizontal direction from a most proximal one of the dielectric pillar structures.
5. The three-dimensional memory device of claim 4 , wherein:
the vertical semiconductor channel comprises a pair of semiconductor channel layers laterally spaced apart along the second horizontal direction by a dielectric core; and
each of the pair of semiconductor channel layers has a minimum thickness at a location that is equidistant from a most proximal pair of dielectric pillar structures among the dielectric pillar structures.
6. The three-dimensional memory device of claim 4 , wherein:
the vertical semiconductor channel comprises a single semiconductor channel layer contacting the pair of memory films and embedding a dielectric core therein; and
the dielectric core has a maximum lateral dimension along the second horizontal direction at a location that is equidistant from a most proximal pair of dielectric pillar structures among the dielectric pillar structures.
7. A three-dimensional memory device comprising:
alternating stacks of insulating strips and electrically conductive strips located over a substrate and laterally spaced apart among one another by line trenches laterally extending along a first horizontal direction and spaced apart among one another along a second horizontal direction; and
an alternating two-dimensional array of memory stack assemblies and dielectric pillar structures located in the line trenches,
wherein each memory stack assembly comprises a vertical semiconductor channel and a pair of memory films laterally spaced apart along the second horizontal direction;
wherein the vertical semiconductor channel comprises a single crystalline semiconductor material or a polycrystalline semiconductor material having an average grain size greater than 20 nm; and
wherein the vertical semiconductor channel comprises the single crystalline semiconductor material that is epitaxially aligned to a single crystalline semiconductor material of the substrate.
8. The three-dimensional memory device of claim 7 , wherein the vertical semiconductor channel comprises a horizonal semiconductor channel portion contacting the semiconductor substrate and a pair of vertical semiconductor channel portions contacting a respective one of the pair of memory films.
9. A three-dimensional memory device comprising:
alternating stacks of insulating strips and electrically conductive strips located over a substrate and laterally spaced apart among one another by line trenches laterally extending along a first horizontal direction and spaced apart among one another along a second horizontal direction; and
an alternating two-dimensional array of memory stack assemblies and dielectric pillar structures located in the line trenches,
wherein each memory stack assembly comprises a vertical semiconductor channel and a pair of memory films laterally spaced apart along the second horizontal direction;
wherein the vertical semiconductor channel comprises a single crystalline semiconductor material or a polycrystalline semiconductor material having an average grain size greater than 20 nm; and
wherein each memory film is a portion of a memory film layer that contacts at least three dielectric pillar structures that are laterally spaced apart along the first horizontal direction.