IP Library Granted Patent US 11,009,930
Granted Patent B2
US 11,009,930 · App. 16/033,061 · Granted May 18, 2021

Automatic USB host detection and port configuration

Inventors: Jeffrey Hunt (Glendale, AZ); Andrew Rogers (Tempe, AZ)
Assignee: MICROCHIP TECHNOLOGY INCORPORATED
G06F1/266G06F13/4282G06F2213/0042
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Quick Facts
Patent No.
US 11,009,930
App. No.
16/033,061
Granted
May 18, 2021
Kind
B2
Abstract

A universal serial bus (USB) hub includes detection circuits for a D− and a D+ connection of a USB port and a control circuit. The control circuit is configured to disable, detection circuits, respective impedances. After disabling the respective impedances, the USB hub is further configured to detect, at the detection circuits, respective values from the D+ connection and the D− connection. The USB hub is further configured to, based upon the respective values, switch the USB port between a device port configuration and a host port configuration.

Claims (66)

1. A universal serial bus (USB) hub, comprising:

a first detection circuit for a D+ connection of a USB port;

a second detection circuit for a D− connection of the USB port; and

a control circuit configured to:

disable, at the first detection circuit and the second detection circuit, respective impedances;

after disabling the respective impedances, detect, at the first detection circuit and the second detection circuit, respective values from the D+ connection and the D− connection; and

based upon the respective values, switch the USB port between a device port configuration and a host port configuration;

in a host check mode:

disable the respective impedances;

enable respective current sources in the first detection circuit and the second detection circuit; and

after disabling the respective impedances and enabling the respective current sources, detect the respective values; and

in a device check mode:

enable the respective impedances;

disable respective current sources in the first detection circuit and the second detection circuit; and

after enabling the respective impedances and disabling the respective current sources, detect the respective values;

identify that the respective values are zero in an instance of the device check mode; and

based upon the identification that the respective values are zero in the instance of the device check mode, enter the host check mode.

2. The USB hub of claim 1 , wherein the control circuit is configured to switch the USB port between the device port configuration and the host port configuration without a command from a host connected to the USB hub.

3. The USB hub of claim 1 , wherein the control circuit is further configured to switch the USB port from the device port configuration to the host port configuration based upon the respective values resulting from disabling the respective impedances.

4. The USB hub of claim 1 , wherein the control circuit is further configured to enable, at the first detection circuit and the second detection circuit, respective current sources.

5. The USB hub of claim 4 , wherein the control circuit is further configured to, after enabling the respective current sources and disabling the respective impedances, detect the respective values.

6. The USB hub of claim 1 , wherein the control circuit is configured to determine that a USB host has connected to the USB port based upon a zero value in each of the respective values.

7. A method for operating a universal serial bus (USB) hub, comprising:

operating a first detection circuit to detect a D+ connection of a USB port;

operating a second detection circuit to detect a D− connection of the USB port; and

through a control circuit:

disabling, at the first detection circuit and the second detection circuit, respective impedances;

after disabling the respective impedances, detecting, at the first detection circuit and the second detection circuit, respective values from the D+ connection and the D− connection;

based upon the respective values, switching the USB port between a device port configuration and a host port configuration;

in a host check mode:

disabling the respective impedances;

enabling respective current sources in the first detection circuit and the second detection circuit; and

after disabling the respective impedances and enabling the respective current sources, detect the respective values; and

in a device check mode:

enabling the respective impedances;

disabling respective current sources in the first detection circuit and the second detection circuit; and

after enabling the respective impedances and disabling the respective current sources, detecting the respective values;

identifying that the respective values are zero in an instance of the device check mode; and

based upon the identification that the respective values are zero in the instance of the device check mode, entering the host check mode.

8. The method of claim 7 , further comprising switching the USB port between the device port configuration and the host port configuration without a command from a host connected to the USB hub.

9. The method of claim 7 further comprising switching the USB port from the device port configuration to the host port configuration based upon the respective values resulting from disabling the respective impedances.

10. The method of claim 7 , further comprising enabling, at the first detection circuit and the second detection circuit, respective current sources.

11. The method of claim 10 , further comprising switching, after enabling the respective current sources and disabling the respective impedances, detecting the respective values.

12. The method of claim 7 , further comprising determining that a USB host has connected to the USB port based upon a zero value in each of the respective values.

13. An article of manufacture, comprising a non-transitory memory including instructions, the instructions, when loaded and executed by a processor, configure the processor to:

operate a first detection circuit to detect a D+ connection of a USB port;

operate a second detection circuit to detect a D− connection of the USB port; and

through a control circuit:

disable, at the first detection circuit and the second detection circuit, respective impedances;

after disabling the respective impedances, detect, at the first detection circuit and the second detection circuit, respective values from the D+ connection and the D− connection; and

based upon the respective values, switch the USB port between a device port configuration and a host port configuration;

in a host check mode:

disable the respective impedances;

enable respective current sources in the first detection circuit and the second detection circuit; and

after disabling the respective impedances and enabling the respective current sources, detect the respective values; and

in a device check mode:

enable the respective impedances;

disable respective current sources in the first detection circuit and the second detection circuit; and

after enabling the respective impedances and disabling the respective current sources, detect the respective values;

identify that the respective values are zero in an instance of the device check mode; and

based upon the identification that the respective values are zero in the instance of the device check mode, enter the host check mode.

14. The article of claim 13 , further comprising instructions to cause the processor to switch the USB port between the device port configuration and the host port configuration without a command from a host connected to the USB hub.

15. The article of claim 13 , further comprising instructions to cause the processor to switch the USB port from the device port configuration to the host port configuration based upon the respective values resulting from disabling the respective impedances.

16. The article of claim 13 , further comprising instructions to cause the processor to enable, at the first detection circuit and the second detection circuit, respective current sources.

17. The article of claim 16 , further comprising instructions to cause the processor to, after enabling the respective current sources and disabling the respective impedances, detect the respective values.

18. The article of claim 13 , further comprising instructions to cause the processor to determine that a USB host has connected to the USB port based upon a zero value in each of the respective values.

Assignments (13)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0335 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059263/0001 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 058214/0625 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 052856/0909 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 30, 2019
From: HUNT, JEFFREY; ROGERS, ANDREW
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 048189/0600 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 11, 2018
From: HUNT, JEFFREY; ROGERS, ANDREW
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 046529/0317 →
Continuity (2)
Provisional Application 62662902 · Apr 26, 2018
Related Publication 20190332152A1 · Oct 31, 2019