IP Library Granted Patent US 10,553,336
Granted Patent B2
US 10,553,336 · App. 16/034,423 · Granted Feb 4, 2020

Thin-film resistor (TFR) module with top-side interconnects connected to reduced TFR ridges and manufacturing methods

Inventors: Yaojian Leng (Portland, OR); Justin Sato (West Linn, OR); Greg Stom (Rhododendron, OR)
Assignee: MICROCHIP TECHNOLOGY INCORPORATED
H01C17/075H01C1/142H01C7/006H01C17/006H01C17/288
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Quick Facts
Patent No.
US 10,553,336
App. No.
16/034,423
Granted
Feb 4, 2020
Kind
B2
Abstract

A method for manufacturing a thin film resistor (TFR) module in an integrated circuit (IC) structure is provided. A TFR trench may be formed in an oxide layer. A resistive TFR layer may be deposited over the structure and extending into the trench. Portions of the TFR layer outside the trench may be removed by CMP to define a TFR element including a laterally-extending TFR bottom region and a plurality of TFR ridges extending upwardly from the laterally-extending TFR bottom region. At least one CMP may be performed to remove all or portions of the oxide layer and at least a partial height of the TFR ridges. A pair of spaced-apart metal interconnects may then be formed over opposing end regions of the TFR element, wherein each metal interconnect contacts a respective upwardly-extending TFR ridge, to thereby define a resistor between the metal interconnects via the TFR element.

Claims (45)

1. A method for manufacturing a thin film resistor (TFR) module in an integrated circuit (IC) structure, the method comprising:

forming a trench in an integrated circuit structure;

depositing a resistive TFR layer over the integrated circuit structure and extending into the trench;

removing portions of the TFR layer outside the trench to define a TFR element including a laterally-extending TFR bottom region and a plurality of TFR ridges extending upwardly from the laterally-extending TFR bottom region;

performing at least one material removal process to remove at least a partial height of the TFR ridges; and

forming a pair of spaced-apart metal interconnects over opposing end regions of the TFR element by a process including:

depositing a metal layer over the TFR element; and

performing a metal etch to remove portions of the metal layer to thereby define the pair of spaced-apart metal interconnects, wherein the metal etch also removes at least a partial height of at least one TFR ridge uncovered by the metal interconnects,

wherein each metal interconnect contacts a respective upwardly-extending TFR ridge, to thereby define a conductive path between the metal interconnects via the TFR element.

2. The method of claim 1 , wherein the at least one material removal process forms a mound-shaped structure including the TFR element; and

wherein forming the pair of spaced-apart metal interconnects comprises forming the pair of metal interconnects on sloping upper surfaces of the mound-shaped structure.

3. The method of claim 1 , wherein the spaced-apart metal interconnects comprise aluminum.

4. The method of claim 1 , wherein the spaced-apart metal interconnects are formed in a metal 1 layer.

5. The method of claim 1 , wherein the TFR layer comprises SiCr or SiCCr.

6. The method of claim 1 , further comprising:

prior to removing portions of the TFR layer outside the trench, depositing a nitride cap layer over the TFR layer and extending into the trench; and

wherein the step of removing portions of the TFR layer outside the trench to define the TFR element also removes portions of the nitride cap layer outside the trench.

7. The method of claim 1 , further comprising, prior to forming the metal interconnects, annealing the TFR layer or TFR element to provide a selected temperature coefficient of resistance (TCR).

8. The method of claim 1 , wherein forming a trench in an integrated circuit structure comprises:

forming an oxide layer over a dielectric region; and

forming a trench in the oxide layer.

9. The method of claim 1 , wherein the material removal process comprises a chemical mechanical planarization (CMP).

10. The method of claim 1 , wherein removing portions of the TFR layer outside the trench to define the TFR element comprises performing a chemical mechanical planarization (CMP).

11. A thin film resistor (TFR), comprising:

a resistive TFR element including a laterally-extending TFR bottom region and a pair of TFR ridges extending upwardly from first and second lateral sides of the laterally-extending TFR bottom region;

a non-conductive structure adjacent each upwardly-extending TFR ridge, each non-conductive structure defining a sloping top surface that slopes downwardly in a direction away from a center of the TFR element, the sloping top surface being non-parallel and non-perpendicular with respect to the laterally-extending TFR bottom region;

a pair of metal interconnects formed over the TFR element, wherein each metal interconnect:

is positioned over a respective non-conductive structure adjacent a respective upwardly-extending TFR ridge;

extends obliquely over the sloping top surface of the respective non-conductive structure, such that each metal interconnect extends non-parallel and non-perpendicular with respect to the laterally-extending TFR bottom region; and

contacts the respective upwardly-extending TFR ridge;

such that a conductive path is defined between the metal interconnects via the upwardly-extending TFR ridges and the laterally-extending TFR bottom region.

12. The thin film resistor of claim 11 , wherein the metal interconnects comprise aluminum.

13. The thin film resistor of claim 11 , wherein the TFR element comprises a damascene-type element formed in a trench.

14. The thin film resistor of claim 11 , wherein the metal interconnects are formed in a metal 1 layer.

15. The thin film resistor of claim 11 , wherein the TFR element comprises SiCr or SiCCr.

16. The thin film resistor of claim 11 , wherein the non-conductive structure adjacent each upwardly-extending TFR ridge comprises a nitride region located laterally between the pair of upwardly-extending TFR ridges and over the laterally-extending TFR bottom region.

17. The thin film resistor of claim 11 , wherein the non-conductive structure adjacent each upwardly-extending TFR ridge comprises an oxide region on a first side of the respective upwardly-extending TFR ridge and a nitride region on a second side of the respective upwardly-extending TFR ridge.

18. A method for manufacturing a thin film resistor (TFR) module in an integrated circuit (IC) structure, the method comprising:

forming a trench in an integrated circuit structure;

depositing a resistive TFR layer over the integrated circuit structure and extending into the trench;

depositing a nitride cap layer over the TFR layer, the nitride layer extending downwardly into the trench to cover a portion of the TFR layer in the trench and also extending outside the trench to cover portions of the TFR layer outside the trench;

removing the portions of the nitride cap layer outside the trench and the portions of the TFR layer outside the trench to define a TFR element including a laterally-extending TFR bottom region and a plurality of TFR ridges extending upwardly from the laterally-extending TFR bottom region;

performing at least one material removal process to remove at least a partial height of the TFR ridges; and

forming a pair of spaced-apart metal interconnects over opposing end regions of the TFR element, wherein each metal interconnect contacts a respective upwardly-extending TFR ridge, to thereby define a conductive path between the metal interconnects via the TFR element.

19. The method of claim 18 , wherein the removing step leaves at least a partial thickness of the portion of the nitride layer in the trench covering the portion of the TFR layer in the trench.

Assignments (13)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0335 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059263/0001 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 058214/0625 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 052856/0909 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 13, 2018
From: LENG, YAOJIAN; SATO, JUSTIN; STOM, GREG
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 046341/0056 →