Transistor devices having source/drain structure configured with high germanium content portion
Techniques are disclosed for forming column IV transistor devices having source/drain regions with high concentrations of germanium, and exhibiting reduced parasitic resistance relative to conventional devices. In some example embodiments, the source/drain regions each includes a thin p-type silicon or germanium or SiGe deposition with the remainder of the source/drain material deposition being p-type germanium or a germanium alloy (e.g., germanium:tin or other suitable strain inducer, and having a germanium content of at least 80 atomic % and 20 atomic % or less other components). In some cases, evidence of strain relaxation may be observed in the germanium rich cap layer, including misfit dislocations and/or threading dislocations and/or twins. Numerous transistor configurations can be used, including both planar and non-planar transistor structures (e.g., FinFETs and nanowire transistors), as well as strained and unstrained channel structures.
1. An integrated circuit device, comprising:
a semiconductor body comprising at least one of silicon and germanium;
a gate structure at least above the semiconductor body, the gate structure including a gate electrode and a gate dielectric between the semiconductor body and the gate electrode;
a source structure or drain structure adjacent the semiconductor body, the source structure or drain structure including a first portion and a second portion, the first portion comprising at least one of silicon and germanium, and the second portion comprising a p-type dopant, germanium, and tin, the second portion having a germanium concentration in excess of 80 atomic % and a tin concentration in the range of 1 atomic % to 20 atomic %, wherein the first portion is thinner than the second portion; and
a contact structure on the second portion of the source structure or drain structure.
2. The device of claim 1 wherein the p-type dopant is gallium.
3. The device of claim 1 wherein the tin concentration is in the range of 3 atomic % to 8 atomic %.
4. The device of claim 1 wherein in addition to the p-type dopant, the second portion consists essentially of germanium and tin, and wherein the tin concentration is in the range of 3 atomic % to 8 atomic %.
5. The device of claim 1 wherein in addition to the p-type dopant, the second portion consists essentially of germanium, silicon, and tin, and wherein the tin concentration is in the range of 3 atomic % to 8 atomic %.
6. The device of claim 1 wherein the semiconductor body consists essentially of germanium or silicon and germanium, and the first portion of the source structure or drain structure consists essentially of silicon or silicon and germanium.
7. The device of claim 6 further comprising a germanium substrate, wherein the semiconductor body is part of the substrate or distinct from the substrate.
8. The device of claim 1 wherein the semiconductor body comprises a fin or nanowire.
9. An integrated circuit device, comprising:
a semiconductor body comprising at least one of silicon and germanium;
a gate structure on multiple sides of, or wrapped around, the semiconductor body, the gate structure including a gate electrode and a gate dielectric between the semiconductor body and the gate electrode;
a source structure or drain structure adjacent the semiconductor body, the source structure or drain structure including a first portion and a second portion, the first portion comprising at least one of silicon and germanium, and the second portion comprising a p-type dopant and germanium, the second portion having a germanium concentration in excess of 80 atomic %, wherein the first portion is thinner than the second portion, and wherein the first portion is between the second portion and the semiconductor body, and wherein the second portion includes one or more dislocations, the one or more dislocations including at least one of a misfit dislocation, a threading dislocation, or a defect resulting from a change in lattice orientation across a twin plane; and
a contact structure on the second portion of the source structure or drain structure.
10. The device of claim 9 wherein the second portion further comprises tin, the tin concentration being in the range of 3 atomic % to 8 atomic %.
11. The device of claim 9 wherein in addition to the p-type dopant, the second portion consists essentially of germanium.
12. The device of claim 9 wherein in addition to the p-type dopant, the second portion consists essentially of germanium and silicon.
13. The device of claim 9 wherein the semiconductor body consists essentially of silicon, and the first portion of the source structure or drain structure consists essentially of silicon or silicon and germanium.
14. The device of claim 9 wherein the semiconductor body consists essentially of germanium, and the first portion of the source structure or drain structure consists essentially of silicon or silicon and germanium.
15. The device of claim 9 wherein the semiconductor body comprises a fin and the gate structure is on three sides of the fin.
16. The device of claim 9 wherein the one or more dislocations include at least one misfit dislocation.
17. The device of claim 9 wherein the one or more dislocations include at least one threading dislocation.
18. The device of claim 9 wherein the one or more dislocations include at least one defect resulting from a change in lattice orientation across a twin plane.
19. The device of claim 9 wherein the semiconductor body comprises a nanowire and the gate structure wraps around the nanowire.
20. An integrated circuit device, comprising:
a body comprising silicon;
a region comprising silicon, germanium, and a p-type dopant, wherein the region is one of a source region or a drain region; and
one or more layers between the body and the region, wherein the one or more layers comprise silicon and the p-type dopant.
21. The device of claim 20 , wherein the one or more layers consist essentially of a single layer of silicon and the p-type dopant, and wherein the single layer has a thickness in the range of a monolayer to 10 nm between the body and the region.
22. The device of claim 20 , wherein the one or more layers consist essentially of a single layer of silicon and the p-type dopant, and wherein the single layer has a thickness in the range of one to three monolayers between the body and the region.
23. The device of claim 20 , wherein the one or more layers comprise a graded layer, the graded layer including germanium, and wherein germanium content in the graded layer increases from a portion nearest the body to a portion nearest the region, the region including an atomic percent of germanium.
24. The device of claim 20 , wherein the one or more layers comprise a plurality of layers, the plurality of layers including silicon, germanium, and the p-type dopant, germanium content increasing from a layer of the plurality of layers nearest the body to a layer of the plurality of layers nearest the region, the region including an atomic percent of germanium.
25. The device of claim 20 , wherein the body comprises a fin and/or nanowire and consists essentially of silicon, and the region has a germanium concentration in excess of 50 atomic %.