IP Library Granted Patent US 10,643,887
Granted Patent B2
US 10,643,887 · App. 16/037,941 · Granted May 5, 2020

Method of manufacturing damascene thin-film resistor (TFR) in poly-metal dielectric

Inventor: Yaojian Leng (Portland, OR)
Assignee: MICROCHIP TECHNOLOGY INCORPORATED
H01L21/76805H01L21/76802H01L21/76804H01L21/76807H01L23/5228H01L23/53214H01L23/53228H01L28/24
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Quick Facts
Patent No.
US 10,643,887
App. No.
16/037,941
Granted
May 5, 2020
Kind
B2
Abstract

A damascene thin-film resistor (TFR), e.g., a damascene thin-film resistor module formed within a poly-metal dielectric (PMD) layer using a single added mask layer, and a method for manufacturing such a device, are disclosed. A method for manufacturing a TFR structure may include forming a pair of spaced-apart TFR heads formed as self-aligned silicide poly (salicide) structures, depositing a dielectric layer over the salicide TFR heads, patterning and etching a trench extending laterally over at least a portion of each salicide TFR head and exposing a surface of each salicide TFR heads is exposed, and depositing a TFR material into the trench and onto the exposed TFR head surfaces, to thereby form a TFR layer that bridges the pair of spaced-apart TFR heads.

Claims (34)

1. A method for manufacturing a thin film resistor (TFR) structure, the method comprising:

forming a pair of TFR heads spaced apart from each other, each TFR head comprising a self-aligned silicide (salicide) structure;

depositing a dielectric layer over the salicide TFR heads;

patterning a photoresist trench into a photoresist layer using photo lithography, the patterned photoresist trench extending laterally over at least a portion of each salicide TFR head;

etching through the photoresist trench and through at least a portion of the dielectric layer and stopping at the salicide TFR heads to define a single TFR trench, such that a surface of each salicide TFR head is exposed in the single TFR trench; and

depositing a TFR material into the single TFR trench and onto the exposed surfaces of the salicide TFR heads, to thereby form a TFR layer that bridges the pair of spaced-apart salicide TFR heads.

2. The method of claim 1 , wherein the TFR material comprises SiCr.

3. The method of claim 1 , comprising annealing the TFR structure after depositing the TFR material to alter a temperature coefficient of resistance (TCR) of the TFR material.

4. The method of claim 3 , comprising annealing the structure to achieve a TCR of the TFR material to a non-zero TCR value of less than |100 ppm/° C.|.

5. The method of claim 3 , comprising annealing the structure to achieve a TCR of the TFR material to a non-zero TCR value of less than |50 ppm/° C.|.

6. The method of claim 3 , comprising annealing the structure to achieve a TCR of the TFR material to a non-zero TCR value of less than |10 ppm/° C.|.

7. The method of claim 3 , comprising annealing the structure at a temperature in the range of 450° C. to 550° C.

8. The method of claim 1 , further comprising performing a Chemical Mechanical Polishing (CMP) process to remove portions of the TFR material outside the single TFR trench.

9. The method of claim 8 , further comprising, after the removal process to remove portions of the TFR material outside the single TFR trench, forming at least one of a phosphosilicate glass (PSG) layer or an un-doped silicate glass (USG) cap oxide layer over the structure.

10. The method of claim 1 , further comprising forming conductive contacts to contact each salicide TFR head.

11. The method of claim 1 , further comprising conductively connecting the TFR structure to at least one aluminum interconnect.

12. The method of claim 1 , further comprising conductively connecting the TFR structure to at least one copper interconnect.

13. The method of claim 1 , further wherein the TFR layer comprises a continuous TFR region lying in a single horizontal plane and contacting both of the spaced-apart salicide TFR heads.

14. The method of claim 1 , further comprising:

after depositing the dielectric layer over the salicide TFR heads, forming a sacrificial layer over the dielectric layer;

wherein the etching step removes a portion of the sacrificial layer below the photoresist trench; and

after depositing the TFR material to thereby form the TFR layer that bridges the pair of spaced-apart salicide TFR heads, removing (a) portions of the TFR material laterally outside the single TFR trench along with (b) remaining portions of the sacrificial layer.

15. A method for manufacturing a thin film resistor (TFR) structure, the method comprising:

forming a pair of TFR heads spaced apart from each other, each TFR head comprising a self-aligned silicide (salicide) structure;

depositing a dielectric layer over the salicide TFR heads;

patterning a photoresist trench into a photoresist layer using photo lithography, the patterned photoresist trench extending laterally over at least a portion of each salicide TFR head;

etching through the photoresist trench and through at least a portion of the dielectric layer and stopping at the salicide TFR heads, such that a surface of each salicide TFR head is exposed; and

depositing a TFR material into the TFR trench and onto the exposed surfaces of the salicide TFR heads, to thereby form a TFR layer that bridges the pair of spaced-apart salicide TFR heads; and

performing a Chemical Mechanical Polishing (CMP) process to remove portions of the TFR material outside the TFR trench.

16. The method of claim 15 , further comprising, after the removal process to remove portions of the TFR material outside the TFR trench, forming at least one of a phosphosilicate glass (PSG) layer or an un-doped silicate glass (USG) cap oxide layer over the structure.

17. The method of claim 15 , comprising annealing the structure after depositing the TFR material to alter a temperature coefficient of resistance (TCR) of the TFR material.

18. The method of claim 17 , comprising annealing the structure to achieve a TCR of the TFR material to a non-zero TCR value of less than |100 ppm/° C.|.

19. The method of claim 17 , comprising annealing the structure to achieve a TCR of the TFR material to a non-zero TCR value of less than |50 ppm/° C.|.

20. The method of claim 17 , comprising annealing the structure to achieve a TCR of the TFR material to a non-zero TCR value of less than |10 ppm/° C.|.

Assignments (13)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0335 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059263/0001 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 058214/0625 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 052856/0909 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 17, 2018
From: LENG, YAOJIAN
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 046569/0069 →