IP Library › Granted Patent US 10,510,755
Granted Patent B2
US 10,510,755 · App. 16/041,996 · Granted Dec 17, 2019

Semiconductor device and manufacture method thereof

Inventors: Che-Cheng Chang (New Taipei, TW); Chih-Han Lin (Hsinchu, TW); Horng-Huei Tseng (HsinChu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
H01L27/0924H01L21/823821H01L21/823842H01L21/823864H01L27/0886H01L27/092H01L29/0649H01L29/4958H01L29/4966H01L29/517H01L29/518H01L29/66545H01L29/7851H01L29/66636H01L29/7848
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Quick Facts
Patent No.
US 10,510,755
App. No.
16/041,996
Granted
Dec 17, 2019
Kind
B2
Abstract

A semiconductor device includes a semiconductor substrate and at least one gate stack. The gate stack is present on the semiconductor substrate, and the gate stack includes at least one work function conductor and a filling conductor. The work function conductor has a recess therein. The filling conductor includes a plug portion and a cap portion. The plug portion is present in the recess of the work function conductor. The cap portion caps the work function conductor.

Claims (38)

1. A semiconductor device, comprising:

a first gate stack comprising:

a first work function conductor; and

a first filling conductor comprising a plug portion and a cap portion; and

a first gate spacer disposed on a first side of the first gate stack, wherein:

the cap portion overlies an uppermost surface of the first work function conductor, and

a sidewall of the plug portion is spaced apart from a sidewall of the first gate spacer by the first work function conductor.

2. The semiconductor device of claim 1 , wherein a sidewall of the cap portion and a sidewall of the first work function conductor are in direct contact with the sidewall of the first gate spacer.

3. The semiconductor device of claim 1 , wherein the plug portion is between a first portion of the first work function conductor and a second portion of the first work function conductor.

4. The semiconductor device of claim 1 , comprising:

a second work function conductor overlying the first work function conductor.

5. The semiconductor device of claim 1 , comprising a dielectric cap overlying the cap portion.

6. The semiconductor device of claim 1 , comprising a semiconductor fin disposed below the first gate stack.

7. The semiconductor device of claim 4 , wherein the sidewall of the plug portion is spaced apart from the sidewall of the first gate spacer by the second work function conductor.

8. The semiconductor device of claim 4 , wherein the first work function conductor is one of an n-type work function conductor or a p-type work function conductor and the second work function conductor is the other of the n-type work function conductor or the p-type work function conductor.

9. The semiconductor device of claim 5 , wherein the dielectric cap is in direct contact with the sidewall of the first gate spacer.

10. The semiconductor device of claim 5 , wherein cap portion is between the first work function conductor and the dielectric cap.

11. A semiconductor device, comprising:

a first gate spacer and a second gate spacer; and

a gate stack disposed between the first gate spacer and the second gate spacer, the gate stack comprising:

a gate dielectric;

a first work function conductor over the gate dielectric;

a filling conductor over the first work function conductor; and

a dielectric cap, wherein a cap portion of the filling conductor is between an uppermost surface of the first work function conductor and the dielectric cap.

12. The semiconductor device of claim 11 , wherein the filling conductor comprises a plug portion and the cap portion, wherein the plug portion is spaced apart from first gate spacer by the first work function conductor.

13. The semiconductor device of claim 11 , wherein the gate dielectric is in direct contact with the first gate spacer and the second gate spacer.

14. The semiconductor device of claim 11 , comprising:

a second work function conductor between the first work function conductor and the filling conductor.

15. The semiconductor device of claim 12 , wherein the cap portion is in direct contact with the first gate spacer.

16. A method of manufacturing a semiconductor device, the method comprising:

forming a first work function conductor between a first gate spacer and a second gate spacer, wherein the first work function conductor defines a first recess;

recessing the first work function conductor to define a second recess having a second width greater than a first width of the first recess;

forming a filling conductor in the first recess and the second recess; and

recessing the filling conductor to define a third recess.

17. The method of claim 16 , comprising forming a dielectric layer in the third recess.

18. The method of claim 16 , the recessing the filling conductor comprising recessing the filling conductor while maintaining a portion of the filling conductor above an uppermost surface of the first work function conductor.

19. The method of claim 16 , comprising forming a second work function conductor over the first work function conductor prior to the recessing the first work function conductor.

20. The method of claim 16 , wherein the third recess has the second width.

Continuity (4)
Continuation 15722229 · Oct 2, 2017
Continuation 15135476 · Apr 21, 2016
Provisional Application 62297750 · Feb 19, 2016
Related Publication 20180350813A1 · Dec 6, 2018