Split-gate flash memory array with byte erase operation
View Patent ↗A memory device with memory cells in rows and columns, word lines connecting together the control gates for the memory cell rows, bit lines electrically connecting together the drain regions for the memory cell columns, first sub source lines each electrically connecting together the source regions in one of the memory cell rows and in a first plurality of memory cell columns, second sub source lines each electrically connecting together the source regions in one of the memory cell rows and in a second plurality of memory cell columns, first and second source lines, first select transistors each connected between one of first sub source lines and the first source line, second select transistors each connected between one of second sub source lines and the second source line, and select transistor lines each connected to gates of one of the first select transistors and one of the second select transistors.
1. A memory device, comprising:
a plurality of memory cells configured in rows and columns on a semiconductor substrate, wherein each of the memory cells includes:
source and drain regions formed in the substrate and defining a channel region of the substrate extending there between,
a floating gate disposed over and insulated from a first portion of the channel region,
a control gate disposed over and insulated from a second portion of the channel region;
a plurality of word lines each electrically connecting together all of the control gates for one of the rows of the memory cells;
a plurality of bit lines each electrically connecting together the drain regions for one of the columns of the memory cells;
a plurality of first sub source lines each electrically connecting together the source regions of the memory cells that are in one of the rows of the memory cells and are in a first plurality of the columns of the memory cells;
a plurality of second sub source lines each electrically connecting together the source regions of the memory cells that are in one of the rows of the memory cells and are in a second plurality of the columns of the memory cells, wherein the first plurality of the columns is different from the second plurality of the columns;
a first source line and a second source line;
a plurality of first select transistors each connected between one of the first sub source lines and the first source line;
a plurality of second select transistors each connected between one of the second sub source lines and the second source line;
a plurality of select transistor lines each connected to a gate of one of the first select transistors and a gate of one of the second select transistors.
2. The memory device of claim 1 , wherein for each of the select transistor lines, the one of the first select transistors and the one of the second select transistors are connected to the sub source lines for a same row of the memory cells.
3. The memory device of claim 1 , further comprising:
a controller configured to perform an erase operation on a target group of the memory cells which are in the first plurality of columns of the memory cells, are connected to a first of the sub source lines, and are connected to a first of the word lines, by:
applying a positive voltage to the first word line;
applying a positive voltage to a first of the select transistor lines which is connected to the gate of the select transistor that is connected between the second source line and a second of the sub source lines for memory cells which are in the second plurality of columns of the memory cells and are connected to the first word line; and
applying a positive voltage to the second source line.
4. The memory device of claim 3 , wherein the controller is configured to perform the erase operation further by applying a voltage below a threshold voltage of the first and second select transistors to the plurality of select transistor lines except for the first of the select transistor lines.
5. The memory device of claim 1 , wherein:
each of the first sub source lines electrically connects together the source regions of the memory cells that are in a second one of the rows of the memory cells and that are in the first plurality of the columns of the memory cells; and
each of the second sub source lines electrically connects together the source regions of the memory cells that are in a second one of the rows of the memory cells and that are in the second plurality of the columns of the memory cells.
6. A memory device, comprising:
a plurality of memory cells configured in rows and columns on a semiconductor substrate, wherein each of the memory cells includes:
source and drain regions formed in the substrate and defining a channel region of the substrate extending there between,
a floating gate disposed over and insulated from a first portion of the channel region,
a control gate disposed over and insulated from a second portion of the channel region;
a plurality of word lines each electrically connecting together all of the control gates for one of the rows of the memory cells;
a plurality of bit lines each electrically connecting together the drain regions for one of the columns of the memory cells;
a plurality of first sub source lines each electrically connecting together the source regions of the memory cells that are in one of the rows of the memory cells and are in a first plurality of the columns of the memory cells;
a plurality of second sub source lines each electrically connecting together the source regions of the memory cells that are in one of the rows of the memory cells and are in a second plurality of the columns of the memory cells, wherein the first plurality of the columns is different from the second plurality of the columns;
a first source line and a second source line;
a plurality of first select transistors each connected between one of the first sub source lines and the first source line;
a plurality of second select transistors each connected between one of the second sub source lines and the second source line;
a plurality of select transistor lines each connected to a gate of one of the first select transistors and a gate of one of the second select transistors;
a plurality of third select transistors each connected between one of first sub source lines and the first source line;
a plurality of fourth select transistors each connected between one of second sub source lines and the second source line.
7. The memory device of claim 1 , wherein:
for each one of the first sub source lines, all of the source regions electrically connected together by the one first sub source line are for memory cells in only one of the rows of the memory cells; and
for each one of the second sub source lines, all of the source regions electrically connected together by the one second sub source line are for memory cells in only one of the rows of the memory cells.
8. The memory device of claim 1 , further comprising:
a plurality of third sub source lines each electrically connecting together the source regions of the memory cells that are in one of the rows of the memory cells and are in a third plurality of the columns of the memory cells;
a plurality of fourth sub source lines each electrically connecting together the source regions of the memory cells that are in one of the rows of the memory cells and are in a fourth plurality of the columns of the memory cells, wherein the first, second, third and fourth pluralities of the columns are different from each other;
a plurality of third select transistors each connected between one of third sub source lines and the first source line;
a plurality of fourth select transistors each connected between one of fourth sub source lines and the second source line;
wherein each of the select transistor lines is connected to a gate of one of the first select transistors and a gate of one of the second select transistors and a gate of one of the third select transistors and a gate of one of the fourth select transistors.
9. The memory device of claim 1 , further comprising:
a plurality of third sub source lines each electrically connecting together the source regions of the memory cells that are in one of the rows of the memory cells and are in a third plurality of the columns of the memory cells;
a plurality of fourth sub source lines each electrically connecting together the source regions of the memory cells that are in one of the rows of the memory cells and are in a fourth plurality of the columns of the memory cells, wherein the first, second, third and fourth pluralities of the columns are different from each other;
a plurality of third select transistors each connected between one of third sub source lines and the first source line;
a plurality of fourth select transistors each connected between one of fourth sub source lines and the second source line;
wherein each of the select transistor lines is connected to a gate of one of the first select transistors and a gate of one of the second select transistors and a gate of one of the third select transistors and a gate of one of the fourth select transistors;
wherein for each one of the first sub source lines, all of the source regions electrically connected together by the one first sub source line are for memory cells in only one of the rows of the memory cells;
wherein for each one of the second sub source lines, all of the source regions electrically connected together by the one second sub source line are for memory cells in only one of the rows of the memory cells;
wherein for each one of the third sub source lines, all of the source regions electrically connected together by the one third sub source line are for memory cells in only one of the rows of the memory cells; and
wherein for each one of the fourth sub source lines, all of the source regions electrically connected together by the one fourth sub source line are for memory cells in only one of the rows of the memory cells.
10. A memory device, comprising:
a plurality of memory cells configured in rows and columns on a semiconductor substrate, wherein each of the memory cells includes:
source and drain regions formed in the substrate and defining a channel region of the substrate extending there between,
a floating gate disposed over and insulated from a first portion of the channel region,
a control gate disposed over and insulated from a second portion of the channel region;
a plurality of word lines each electrically connecting together all of the control gates for one of the rows of the memory cells;
a plurality of bit lines each electrically connecting together the drain regions for one of the columns of the memory cells;
a plurality of first sub source lines each electrically connecting together the source regions of the memory cells that are in one of the rows of the memory cells and are in a first plurality of the columns of the memory cells;
a plurality of second sub source lines each electrically connecting together the source regions of the memory cells that are in one of the rows of the memory cells and are in a second plurality of the columns of the memory cells, wherein the first plurality of the columns is different from the second plurality of the columns;
a plurality of source lines;
a plurality of first select transistors each connected between one of first sub source lines and one of the source lines;
a plurality of second select transistors each connected between one of second sub source lines and one of the source lines;
a first select transistor line connected to gates of the first select transistors; and
a second select transistor line connected to gates of the second select transistors.
11. The memory device of claim 10 , wherein for each of the source lines, one of the first select transistors connected thereto is connected to one of the first sub source lines for a first row of the memory cells and one of the second select transistors connected thereto is connected to one of the second sub source lines for the first row of the memory cells.
12. The memory device of claim 10 , further comprising:
a controller configured to perform an erase operation on a target group of the memory cells which are in the first plurality of columns of the memory cells, are connected to a first of the sub source lines, and are connected to a first of the word lines, by:
applying a positive voltage to the first word line;
applying a positive voltage to the second select transistor line; and
applying a positive voltage to one of the source lines that is connected to one of the select transistors that is connected to one of the sub source lines for memory cells which are in the second plurality of columns of the memory cells and are connected to the first word line.
13. The memory device of claim 12 , wherein the controller is configured to perform the erase operation further by applying a voltage below a threshold voltage of the first and second select transistors to the first select transistor line.
14. The memory device of claim 10 , wherein:
each of the first sub source lines electrically connects together the source regions of the memory cells that are in a second one of the rows of the memory cells and that are in the first plurality of the columns of the memory cells; and
each of the second sub source lines electrically connects together the source regions of the memory cells that are in a second one of the rows of the memory cells and that are in the second plurality of the columns of the memory cells.
15. The memory device of claim 10 , wherein:
for each one of the first sub source lines, all of the source regions electrically connected together by the one first sub source line are for memory cells in only one of the rows of the memory cells; and
for each one of the second sub source lines, all of the source regions electrically connected together by the one second sub source line are for memory cells in only one of the rows of the memory cells.