Trench-type insulated gate semiconductor device including an emitter trench and an overlapped floating region
A semiconductor device is disclosed having a plurality of gate trenches formed on the surface thereof, each filled with a gate insulating film and a gate electrode. A transistor region is defined between adjacent gate trenches forming a pair, and includes an n + -type emitter region, a p-type base region, and an n − -type drift region disposed lateral to each gate trench in the pair, in order in a depth direction of the gate trench from a front surface side of the semiconductor layer. A p + -type collector region disposed on a back surface side of the semiconductor layer with respect to the n − -type drift region. A plurality of emitter trenches are formed one either side of each of the gate trenches in the pair of gate trenches.
1. A semiconductor device comprising:
a semiconductor layer;
a plurality of gate trenches formed in the semiconductor layer;
a gate electrode filled via a gate insulating film in the plurality of gate trenches;
an n + -type emitter region, a p-type base region, and an n − -type drift region disposed laterally to each gate trench, in order in a depth direction of the gate trench from a front surface side of the semiconductor layer, the n + -type emitter region, the p-type base region, and the n − -type drift region forming a transistor cell region;
a p + -type collector region disposed on a back surface side of the semiconductor layer with respect to the n − -type drift region;
a plurality of emitter trenches formed between the plurality of gate trenches adjacent to each other;
a buried electrode filled via an insulating film in the plurality of emitter trenches, electrically connected with the n + -type emitter region;
a dummy trench formed between each of the gate trenches and each adjacent emitter trench such that the n+-type emitter region, the p-type base region, and the n − -type drift region are formed between the dummy trench and the gate trench;
a buried insulating film filled in the dummy trench and having an upper surface with a portion offset towards a bottom side of the dummy trench with respect to the front surface of the semiconductor layer, for selectively exposing as a contact region a part of the p-type base region at a part from the front surface of the semiconductor layer to the upper surface of the buried insulating film in a side surface of the dummy trench; and
a contact electrode filled in a region over the buried insulating film of the dummy trench, connected to the contact region on the side surface of the dummy trench,
wherein each gate trench is sandwiched between the plurality of emitter trenches such that a non-transistor cell region is formed between each of the gate trenches and each adjacent emitter trench,
wherein the transistor cell region and the non-transistor cell region are formed alternatively along the front surface of the semiconductor layer,
wherein the n + -type emitter region selectively has a pullout portion pulled out in a transverse direction along the front surface of the semiconductor layer from a side surface of the gate trench, and
the semiconductor device further comprising an n-type buffer region disposed between a part of the n − -type drift region and the p + -type collector region.
2. The semiconductor device according to claim 1 , further comprising a p-type region formed between the plurality of emitter trenches, wherein
the p-type region is formed deeper than the p-type base region, and includes an overlap portion that goes around to a lower side of an emitter trench closest to the gate trench out of the plurality of emitter trenches and has an end portion positioned on a side closer to the gate trench with respect to a center in a width direction of the emitter trench, and
wherein a part of the n − -type drift region is disposed below the p-type region.
3. The semiconductor device according to claim 2 , wherein the p-type region includes a p-type floating region in which a floating state is electrically maintained.
4. The semiconductor device according to claim 2 , wherein the p-type region has a bottom portion that bulges to the back surface side of the semiconductor layer with respect to a bottom portion of the emitter trench.
5. The semiconductor device according to claim 1 , wherein each of the plurality of emitter trenches is formed at a same depth as that of each of the plurality of gate trenches.
6. The semiconductor device according to claim 1 , wherein the gate trenches are disposed in adjacent pairs, each in a transverse direction along the front surface of the semiconductor layer, and
each pair of gate trenches are opposed in the transverse direction via the p-type base region that is common thereto.
7. The semiconductor device according to claim 6 , wherein one of the pair of gate trenches is disposed at an interval of 2 μm to 7 μm with respect to the other.
8. The semiconductor device according to claim 1 , wherein the n + -type emitter region has an n-type dopant concentration of 1×10 19 cm −3 to 5×10 20 cm −3 .
9. The semiconductor device according to claim 1 , wherein the p-type base region has a p-type dopant concentration of 1×10 16 cm −3 to 1×10 18 cm −3 .
10. The semiconductor device according to claim 1 , wherein the n − -type drift region has an n-type dopant concentration of 1×10 13 cm −3 to 5×10 14 cm −3 .
11. The semiconductor device according to claim 1 , wherein the p + -type collector region has a p-type dopant concentration of 1×10 15 cm −3 to 2×10 19 cm −3 .
12. The semiconductor device according to claim 1 , wherein the n + -type emitter regions are formed one each along both side surfaces of the gate trench.
13. The semiconductor device according to claim 1 , wherein the pullout portion is disposed spaced at fixed intervals along a longitudinal direction of the gate trench.
14. The semiconductor device according to claim 13 , wherein the pullout portions of the respective n + -type emitter regions are disposed so that one and another end portions are opposed to each other across the gate trench.
15. A semiconductor device comprising:
a semiconductor layer;
a plurality of gate trenches formed in the semiconductor layer;
a gate electrode filled via a gate insulating film in the plurality of gate trenches;
an n + -type emitter region, a p-type base region, and an n − -type drift region disposed laterally to each gate trench, in order in a depth direction of the gate trench from a front surface side of the semiconductor layer, the n + -type emitter region, the p-type base region, and the n − -type drift region forming a transistor cell region;
a p + -type collector region disposed on a back surface side of the semiconductor layer with respect to the n − -type drift region;
a plurality of emitter trenches formed in the semiconductor layer;
a buried electrode filled via an insulating film in the plurality of emitter trenches, electrically connected with the n + -type emitter region;
a dummy trench formed between each of the gate trenches and each adjacent emitter trench such that the n+-type emitter region, the p-type base region, and the n − -type drift region are formed between the dummy trench and the gate trench;
a buried insulating film filled in the dummy trench and having an upper surface with a portion offset towards a bottom side of the dummy trench with respect to the front surface of the semiconductor layer, for selectively exposing as a contact region a part of the p-type base region at a part from the front surface of the semiconductor layer to the upper surface of the buried insulating film in a side surface of the dummy trench; and
a contact electrode filled in a region over the buried insulating film of the dummy trench, connected to the contact region on the side surface of the dummy trench,
wherein each gate trench is sandwiched between the plurality of emitter trenches such that a non-transistor cell region is formed between the gate trench and each emitter trench,
wherein the transistor cell region and the non-transistor cell region are formed alternatively along the front surface of the semiconductor layer,
wherein the n + -type emitter region selectively has a pullout portion pulled out in a transverse direction along the front surface of the semiconductor layer from a side surface of the gate trench, and
the semiconductor device further comprising an n-type buffer region disposed between a part of the n − -type drift region and the p + -type collector region.
16. The semiconductor device according to claim 15 , further comprising a p-type region formed at least one of between the plurality of emitter trenches, between the plurality of gate trenches, and between the emitter trench and the gate trench,
wherein the p-type region is formed deeper than the p-type base region, and
wherein a portion of the n − -type drift region is disposed below the p-type region.
17. A method for manufacturing a semiconductor device comprising:
a step of forming a plurality of gate trenches and emitter trenches in a semiconductor layer;
a step of forming a p-type region between the plurality of emitter trenches so as to include an overlap portion that goes around to a lower side of an emitter trench closest to the gate trench out of the plurality of emitter trenches and has an end portion positioned on a side closer to the gate trench with respect to a center in a width direction of the emitter trench;
a step of filling a gate electrode via a gate insulating film in the plurality of gate trenches;
a step of filling a buried electrode via an insulating film in the plurality of emitter trenches;
a step of forming an n + -type emitter region, a p-type base region, and an n − -type drift region so as to be disposed laterally to each gate trench, in order in a depth direction of the gate trench from a front surface side of the semiconductor layer;
a step of forming a dummy trench between each of the gate trenches and each adjacent emitter trench such that the n+-type emitter region, the p-type base region, and the n − -type drift region are formed between the dummy trench and the gate trench;
a step of filling a buried insulating film in the dummy trench, wherein the buried insulating film has an upper surface with a portion offset towards a bottom side of the dummy trench with respect to the front surface of the semiconductor layer, further wherein the buried insulating film selectively exposes as a contact region a part of the p-type base region at a part from the front surface of the semiconductor layer to the upper surface of the buried insulating film in a side surface of the dummy trench;
a step of filling a contact electrode in a region over the buried insulating film of the dummy trench, wherein the contact electrode connects to the contact region on the side surface of the dummy trench;
a step of forming a n-type buffer region on a back surface side of the semiconductor layer; and
a step of forming a p + -type collector region on a back surface side of the semiconductor layer with respect to the n-type buffer region,
wherein the n + -type emitter region selectively has a pullout portion pulled out in a transverse direction along the front surface of the semiconductor layer from a side surface of the gate trench, and
wherein a part of the n − -type drift region is disposed below the p-type region.
18. The method for manufacturing a semiconductor device according claim 17 , wherein the p-type region is formed by diffusing a p-type dopant implanted into the semiconductor layer in advance of the forming of the plurality of emitter trenches.