IP Library › Granted Patent US 11,101,260
Granted Patent B2
US 11,101,260 · App. 16/051,848 · Granted Aug 24, 2021

Method of forming a dummy die of an integrated circuit having an embedded annular structure

Inventors: Shang-Yun Hou (Jubei, TW); Sung-Hui Huang (Dongshan Township, TW); Kuan-Yu Huang (Taipei, TW); Hsien-Pin Hu (Zhubei, TW); Yushun Lin (Taipei, TW); Heh-Chang Huang (Hsinchu, TW); Hsing-Kuo Hsia (Jhubei, TW); Chih-Chieh Hung (Hsinchu, TW); Ying-Ching Shih (Hsinchu, TW); Chin-Fu Kao (Taipei, TW); Wen-Hsin Wei (Hsinchu, TW); Li-Chung Kuo (Taipei, TW); Chi-Hsi Wu (Hsinchu, TW); Chen-Hua Yu (Hsinchu, TW)
Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
H01L25/50H01L21/4803H01L21/4853H01L23/24H01L23/3128H01L23/49827H01L25/0652H01L25/0655H01L25/18H01L24/11H01L24/13H01L24/16H01L24/29H01L24/32H01L24/73H01L24/81H01L24/92H01L24/97H01L2224/0401H01L2224/1144H01L2224/1145H01L2224/11462H01L2224/11464H01L2224/16145H01L2224/16227H01L2224/16235H01L2224/17181H01L2224/32145H01L2224/32225H01L2224/73204H01L2224/73253H01L2224/81191H01L2224/81815H01L2224/92125H01L2224/92225H01L2224/97H01L2225/06513H01L2225/06517H01L2225/06541H01L2924/14H01L2924/1431H01L2924/1432H01L2924/1434H01L2924/1461H01L2924/15311H01L2924/18161
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Quick Facts
Patent No.
US 11,101,260
App. No.
16/051,848
Granted
Aug 24, 2021
Kind
B2
Abstract

An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.

Claims (57)

1. A method comprising:

attaching an integrated circuit die to a first substrate;

forming a dummy die;

attaching the dummy die to the first substrate adjacent the integrated circuit die;

forming an encapsulant over the first substrate and surrounding the dummy die and the integrated circuit die;

planarizing the encapsulant, the dummy die and the integrated circuit die, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die; and

removing an interior portion of the dummy die, a remaining portion of the dummy die forming an annular structure.

2. The method of claim 1 , wherein forming the dummy die comprises:

patterning a second substrate to form an opening in the second substrate, the opening having an annular shape in a plan view; and

depositing an insulating material in the opening.

3. The method of claim 2 , wherein planarizing the encapsulant, the dummy die and the integrated circuit die comprises exposing the insulating material.

4. The method of claim 2 , wherein removing the interior portion of the dummy die comprises:

removing the insulating material, wherein the dummy die is separated into an interior region and a peripheral region after removing the insulating material; and

picking up the interior region from the first substrate, the peripheral region forming the annular structure.

5. The method of claim 4 , wherein removing the insulating material comprises removing the insulating material using a laser drilling method.

6. The method of claim 1 , wherein the dummy die is attached to the first substrate using an adhesive.

7. The method of claim 1 , further comprises:

placing a functional component within the annular structure; and

bonding the functional component to the first substrate, wherein the functional component and the annular structure have different heights.

8. A method comprising:

attaching an integrated circuit die to a first side of a first substrate;

forming a dummy die, the dummy die comprising a first annular structure within the dummy die;

attaching the dummy die to the first side of the first substrate adjacent the integrated circuit die;

forming a molding compound over the first substrate and surrounding the dummy die and the integrated circuit die, a top surface of the molding compound being substantially level with a topmost surface of the dummy die, a topmost surface of the first annular structure, and a topmost surface of the integrated circuit die;

removing the first annular structure, the dummy die being separated into an interior region and a peripheral annular region after removing the first annular structure;

detaching the interior region of the dummy die from the first substrate, the peripheral annular region of the dummy die forming a second annular structure;

placing a functional component on the first side of the first substrate within the second annular structure; and

attaching the functional component to the first side of the first substrate.

9. The method of claim 8 , wherein forming the dummy die comprises:

patterning a second substrate to form an opening in the second substrate, the opening having an annular shape in a plan view; and

depositing an insulating material in the opening to form the first annular structure.

10. The method of claim 8 , wherein removing the first annular structure comprises performing a laser drilling process.

11. The method of claim 8 , wherein the dummy die is attached to the first side of the first substrate using an adhesive.

12. The method of claim 8 , wherein the functional component and the second annular structure have different heights.

13. The method of claim 8 , further comprising forming a plurality of connectors on a second side of the first substrate, the second side of the first substrate being opposite the first side of the first substrate.

14. The method of claim 8 , wherein the first substrate comprises an interposer.

15. A method comprising:

attaching a first integrated circuit die to a first side of a first substrate;

attaching a second integrated circuit die to the first side of the first substrate adjacent the first integrated circuit die;

forming a dummy die, the dummy die comprising:

an interior region;

a first annular structure surrounding the interior region; and

a peripheral annular region surrounding the first annular structure;

attaching the dummy die to a top surface of the second integrated circuit die;

encapsulating the first integrated circuit die, the second integrated circuit die and the dummy die in a molding compound;

planarizing the molding compound to expose a top surface of the dummy die, a top surface of the first annular structure and a top surface of the first integrated circuit die;

removing the first annular structure;

removing the interior region of the dummy die to expose the top surface of the second integrated circuit die;

placing a functional component within the peripheral annular region of the dummy die; and

electrically coupling the functional component to the second integrated circuit die.

16. The method of claim 15 , wherein a height of the functional component is greater than a height of the first annular structure.

17. The method of claim 15 , wherein the first annular structure comprises an insulating material.

18. The method of claim 15 , wherein forming the dummy die comprises:

etching a second substrate to form an opening in the second substrate, the opening having an annular shape in a plan view; and

filling the opening with an insulating material to form the first annular structure.

19. The method of claim 18 , wherein a ratio of a width of the opening to a depth of the opening is between about 0.35 and about 0.7.

20. The method of claim 15 , wherein removing the first annular structure comprises etching the first annular structure.

Assignments (2)
CORRECTIVE ASSIGNMENT TO CORRECT THE SECOND INVENTOR'S NAME PREVIOUSLY RECORDED ON REEL 046525 FRAME 0205. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT OF ASSIGNOR'S INTEREST. Recorded May 25, 2021
From: HOU, SHANG-YUN; HUANG, SUNG-HUI; HUANG, KUAN-YU; HU, HSIEN-PIN; WU, CHI-HSI; YU, CHEN-HUA; SHIH, YING-CHING; KAO, CHIN-FU; WEI, WEN-HSIN; KUO, LI-CHUNG; LIN, YUSHUN; HUANG, HEH-CHANG; HSIA, HSING-KUO; HUNG, CHIH-CHIEH
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 056392/0141 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 1, 2018
From: HOU, SHANG-YUN; HUI, HUANG SUNG; HUANG, KUAN-YU; HU, HSIEN-PIN; WU, CHI-HSI; YU, CHEN-HUA; SHIH, YING-CHING; KAO, CHIN-FU; KUO, LI-CHUNG; LIN, YUSHUN; HUANG, HEH-CHANG; HSIA, HSING-KUO; HUNG, CHIH-CHIEH; WEI, WEN-HSIN
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 046525/0205 →
Continuity (2)
Provisional Application 62625062 · Feb 1, 2018
Related Publication 20190237454A1 · Aug 1, 2019
Cited By (1)
US 12,261,150