Multi-phase parallelable constant on time buck controller with phase interleaving ensured by ripple injection
View Patent ↗A multiple-phase parallelable constant on time (COT) buck controller, a first phase containing a first memory bit and a second phase containing a second memory bit. The COT buck controller includes a first converter comprising a first constant T ON generator configured to sense and deliver a first T ON request when the first memory bit is in a logic one state, and a second converter connected in parallel with the first converter, the second converter comprising a second constant T ON generator configured to sense and deliver a second T ON request when the second memory bit is in the logic one state, only one of the first memory bit and the second memory bit being in the logic one state thus generating activity in a daisy chain ring where each of the first converter and the second converter senses and delivers a corresponding T ON request in a sequential manner.
1. A multiple-phase parallelable constant on time (COT) buck controller, a first phase containing a first memory bit and a second phase containing a second memory bit, the COT buck controller comprising:
a first converter comprising a first constant T ON generator configured to sense and deliver a first T ON request when the first memory bit is in a logic one state; and
a second converter connected in parallel with the first converter, the second converter comprising a second constant T ON generator configured to sense and deliver a second T ON request when the second memory bit is in a logic one state,
only one of the first memory bit and the second memory bit being in the logic one state thus generating activity in a daisy chain ring wherein each of the first converter and the second converter senses and delivers a corresponding T ON request in a sequential manner.
2. The COT buck controller of claim 1 , further comprising an error amplifier and an error comparator, each configured to receive a feedback signal from a feedback pin, the feedback signal including an external ripple injection signal, the error comparator further configured to:
compare the feedback signal with a first reference signal; and
generate a T ON request based on the comparison of the feedback signal with the first reference signal.
3. The COT buck controller of claim 1 , the first converter further comprising a first AND gate and the second converter further comprising a second AND gate, wherein when the first memory bit is in the logic one state, the first AND gate delivers the first T ON request to the first constant T ON generator and when the second memory bit is in the logic one state, the second AND gate delivers the second T ON request to the second constant T ON generator.
4. The COT buck controller of claim 2 , further comprising an inverter that utilizes a ground feedback sense signal to generate a logic signal for determining if the COT buck controller is a master or a slave where more than one COT buck controllers are paralleled.
5. The COT buck controller of claim 4 , wherein if the COT buck controller is designated as a master, the error amplifier and the error comparator are activated, and if the COT buck controller is designated as a slave, the error amplifier and the error comparator are disabled.
6. The COT buck controller of claim 4 , further comprising a multiplexer for allowing configuration of each COT buck controller as either a master or a slave where more than one COT buck controllers are paralleled, the multiplexer configured to distribute the T ON request from the master to each slave through an ONR signal.
7. The COT buck controller of claim 1 , further comprising an input control logic signal, and an output control logic signal which allow multiple phases to be paralleled and work in a daisy chain configuration ring.
8. The COT buck controller of claim 1 , further comprising an OR gate configured to sum a first injected ripple current signal from the first converter and a second injected ripple current signal from the second converter to produce an external injection ripple signal distributed to a feedback pin through the OR gate.
9. A method of paralleling COT buck converters, the method comprising:
sensing and delivering, by a first converter, a first T ON request when a first memory bit in a first phase is in a logic one state; and
sensing and delivering, by a second converter in parallel with the first converter, a second T ON request when a second memory bit in a second phase is the logic one state;
only one of the first memory bit and the second memory bit being in the logic one state thus generating activity in a daisy chain ring wherein each of the first converter and the second converter senses and delivers a corresponding T ON request in a sequential manner.
10. The method of claim 9 , further comprising:
receiving a feedback signal, the feedback signal including an external ripple injection signal;
comparing the feedback signal with a first reference signal; and
generating a T ON request based on the comparison of the feedback signal with the first reference signal.
11. The method of claim 9 , further comprising:
delivering, by a first AND gate, the first T ON request to the first constant T ON generator when the first memory bit is in the logic one state; and
delivering, by a second AND gate, the second T ON request to the second constant T ON generator when the second memory bit is in the logic one state.
12. The method of claim 9 , further comprising:
allowing for paralleling of the first converter and the second converter; and
allowing configuration of the COT buck controller as one of a master or a slave.
13. The method of claim 12 , further comprising using a ground feedback sense signal to generate a logic signal for determining if the COT buck controller is a master or a slave where more than one COT buck controllers are paralleled.
14. The method of claim 12 , wherein if the COT buck controller is designated as a master, activating an error amplifier and an error comparator, and if the COT buck controller is designated as a slave, disabling the error amplifier and the error comparator.
15. The method of claim 12 , further comprising:
configuring each COT buck controller as either a master or a slave where more than one COT buck controllers are paralleled; and
distributing the T ON request from the master to each slave through an ONR signal.
16. The method of claim 9 , further comprising providing an input control logic signal, and an output control logic signal which allow multiple phases to be paralleled and work in a daisy chain configuration ring.
17. The method of claim 9 , further comprising summing, by an OR gate, a first injected ripple current signal from the first converter and a second injected ripple current signal from the second converter to produce an external injection ripple signal distributed in a feedback pin through the OR gate.
18. The method of claim 17 , wherein the external injection ripple signal corresponds to one of the first memory bit and the second memory bit being in the logic one state.
19. A method of using calibrated injection ripple internally or externally generated for single converters or multiphase converters in order to generate a constant ripple in a feedback pin independent of V IN , V OUT or duty cycle thus providing COT converters increased precision, stability and duty cycle.