Semiconductor device and method for fabricating the same
A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a magnetic tunneling junction (MTJ) on the first IMD layer; forming a liner on the MTJ and the first IMD layer; removing part of the liner to form a spacer adjacent to the MTJ; and forming a second IMD layer on the first IMD layer.
1. A method for fabricating semiconductor device, comprising:
forming a first inter-metal dielectric (IMD) layer on a substrate;
forming a metal interconnection in the first IMD layer;
forming a magnetic tunneling junction (MTJ) stack on the first IMD layer and the metal interconnection;
removing the MTJ stack, the first IMD layer, and the metal interconnection to form a MTJ directly on the metal interconnection, wherein a top surface of the first IMD layer adjacent to two sides of the MTJ comprises a curve
forming a liner on the MTJ and the first IMD layer;
removing part of the liner to form a spacer adjacent to the MTJ, wherein a sidewall of the spacer is aligned with a sidewall of the metal interconnection; and
forming a second IMD layer on the first IMD layer.
2. The method of claim 1 , further comprising performing an ion beam etching (IBE) process to remove part of the MTJ stack.
3. The method of claim 2 , further comprising performing the IBE process to remove part of the first IMD layer and part of the metal interconnection so that a top surface of the first IMD layer is lower than a top surface of the metal interconnection.
4. The method of claim 3 , wherein a top surface of the first IMD layer comprises a curve.
5. The method of claim 3 , further comprising performing the IBE process to remove part of the metal interconnection for forming a first slanted sidewall and a second slanted sidewall.
6. The method of claim 5 , further comprising forming the liner on the MTJ, the first slanted sidewall, and the second slanted sidewall.
7. The method of claim 6 , further comprising removing part of the liner to form the spacer on the first slanted sidewall and the second slanted sidewall.
8. A semiconductor device, comprising:
a first inter-metal dielectric (IMD) layer on a substrate;
a magnetic tunneling junction (MTJ) on the first IMD layer;
a metal interconnection under the MTJ and in the first IMD layer, wherein the metal interconnection comprises a first slanted sidewall and a second slanted sidewall; and
a spacer around the MTJ and on the first slanted sidewall and the second slanted sidewall, wherein a sidewall of the spacer is aligned with a sidewall of the metal interconnection and the spacer contacts the first slanted sidewall and the second slanted sidewall directly.
9. The semiconductor device of claim 8 , wherein a top surface of the first IMD layer comprises a curve.
10. The semiconductor device of claim 8 , further comprising a second IMD layer on the first IMD layer and around the spacer.
11. The semiconductor device of claim 8 , wherein the metal interconnection comprises a third slanted sidewall connected to the first slanted sidewall and a fourth slanted sidewall connected to the second slanted sidewall.
12. The semiconductor device of claim 11 , wherein the first slanted sidewall and the third slanted sidewall comprise a V-shape.
13. The semiconductor device of claim 11 , wherein the second slanted sidewall and the fourth slanted sidewall comprise a V-shape.