IP Library › Granted Patent US 12,408,559
Granted Patent B2
US 12,408,559 · App. 18/587,823 · Granted Sep 2, 2025

Semiconductor device and method for fabricating the same

Inventors: Hui-Lin Wang (Taipei, TW); Wei Chen (Tainan, TW); Po-Kai Hsu (Tainan, TW); Yu-Ping Wang (Hsinchu, TW); Hung-Yueh Chen (Hsinchu, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H10N50/01H01F10/3254H01F10/329H10N50/80
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Quick Facts
Patent No.
US 12,408,559
App. No.
18/587,823
Granted
Sep 2, 2025
Kind
B2
Abstract

A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first metal interconnection and a second metal interconnection in the first IMD layer; forming a channel layer on the first metal interconnection and the second metal interconnection; forming a magnetic tunneling junction (MTJ) stack on the channel layer; and removing the MTJ stack to form a MTJ.

Claims (25)

1. A method for fabricating a semiconductor device, comprising:

forming a first inter-metal dielectric (IMD) layer on a substrate;

forming a first metal interconnection and a second metal interconnection in the first IMD layer;

forming a channel layer on the first metal interconnection and the second metal interconnection,

forming a magnetic tunneling junction (MTJ) stack on the channel layer; and

removing part of the MTJ stack and part of the channel layer to form an MTJ, wherein a sidewall of the MTJ comprises a curve.

2. The method of claim 1 , wherein the step of forming the channel layer comprises:

forming a dielectric layer on the first IMD layer;

removing the dielectric layer to form an opening;

forming a first channel layer and a second channel layer in the opening; and

planarizing the first channel layer and the second channel layer, wherein the first channel layer comprises a U-shape.

3. The method of claim 2 , further comprising:

forming the MTJ stack on the first channel layer and the second channel layer; and

removing the MTJ stack, the second channel layer, and the first channel layer.

4. The method of claim 2 , further comprising removing the MTJ stack, the second channel layer, the first channel layer, and the dielectric layer after forming the MTJ stack.

5. The method of claim 2 , wherein the first channel layer and the second channel layer comprise different materials.

6. The method of claim 2 , wherein the first channel layer and the second channel layer comprise different etching rates.

7. The method of claim 2 , further comprising:

forming a cap layer on the MTJ, the channel layer, and the dielectric layer; and

forming a second IMD layer on the cap layer.

8. The method of claim 7 , wherein the cap layer and the dielectric layer comprise different materials.

9. The method of claim 1 , wherein the MTJ comprises:

a free layer on the channel layer;

a barrier layer on the free layer; and

a pinned layer on the barrier layer.

Priority Claims (1)
CN 202010360779.3 · Apr 30, 2020 · national
Continuity (3)
Continuation 17857185 · Jul 5, 2022
Division 16884060 · May 27, 2020
Related Publication 20240196756A1 · Jun 13, 2024
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