Fin structures
The present disclosure relates to semiconductor structures and, more particularly, to fin structures and methods of manufacture. The structure includes: a plurality of fin structures formed of substrate material; a semiconductor material located between selected fin structures of the plurality of fin structures; and isolation regions within spaces between the plurality of fin structures.
1. A structure, comprising:
a plurality of fin structures formed of substrate material;
a semiconductor material located between selected fin structures of the plurality of fin structures; and
isolation regions within spaces between the plurality of fin structures,
wherein the isolation regions are shallow trench isolation regions which are above the semiconductor material between the selected fin structures of the plurality of fin structures, wherein
the semiconductor material is non-consumed within selected spaces between the plurality of fin structures,
the selected spaces between the selected fin structures of the plurality of fin structures each have a width “x” which is smaller than spaces between remaining fin structures of the plurality of fin structures, and
the spaces between the remaining selected fin structures of the plurality of fin structures are devoid of the semiconductor material.
2. The structure of claim 1 , further comprising an insulator liner covering the plurality of fin structures.
3. The structure of claim 2 , wherein the insulator liner is oxide.
4. The structure of claim 1 , wherein the semiconductor material is at a height lower than a height of the plurality of fin structures.
5. The structure of claim 1 , wherein the semiconductor material is positioned to prevent bending of the plurality of fin structures.
6. The structure of claim 1 , wherein the semiconductor material is Si.
7. A structure, comprising:
a plurality of fin structures;
a dielectric liner directly lining the plurality of fin structures;
semiconductor material on the dielectric liner between selected fin structures of the plurality of fin structures; and
shallow trench isolation regions above the semiconductor material between the selected fin structures of the plurality of fin structures and which are below a top surface of the plurality of fin structures, wherein
the semiconductor material is non-consumed within spaces between the selected fin structure of the plurality of fin structures, and
the spaces between the selected fin structures of the plurality of fin structures each have a width “x” which is smaller than spaces between other fin structures of the plurality of fin structures which do not have the semiconductor material therebetween.
8. The structure of claim 7 , further comprising a layer of SiO 2 on the dielectric material between the selected fin structures and the other fin structures.
9. The structure of claim 7 , wherein the shallow trench isolation regions are in direct contact with the semiconductor material and a dielectric material between the selected fin structures of the plurality of fin structures.
10. A structure, comprising:
a plurality of fin structures;
a dielectric liner directly lining the plurality of fin structures;
semiconductor material on the dielectric liner between selected fin structures of the plurality of fin structures; and
shallow trench isolation regions above the semiconductor material between the selected fin structures of the plurality of fin structures and which are below a top surface of the plurality of fin structures, wherein
the shallow trench isolation regions are in direct contact with the semiconductor material and a dielectric material between the selected fin structures of the plurality of fin structures, and
the shallow trench isolation regions are in direct contact with the dielectric material between the other of the plurality of fin structures which do not have the semiconductor material therebetween.