IP Library Granted Patent US 10,903,148
Granted Patent B2
US 10,903,148 · App. 16/058,782 · Granted Jan 26, 2021

High performance multi-component electronics power module

Inventor: Man Kit Lam (Colorado Springs, CO)
Assignee: MICROCHIP TECHNOLOGY INCORPORATED
H01L23/49568H01L21/4825H01L21/4828H01L21/565H01L23/3107H01L23/4952H01L23/49513H01L23/49524H01L23/49548H01L23/49562H01L23/49575H01L23/49582H01L23/49589H01L25/16H01L25/50H01L24/16H01L24/32H01L24/48H01L24/73H01L2224/16258H01L2224/32245H01L2224/48175H01L2224/73265H01L2924/18161
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Quick Facts
Patent No.
US 10,903,148
App. No.
16/058,782
Granted
Jan 26, 2021
Kind
B2
Abstract

Methods are provided for forming an IC power package including a power MOSFET device, a microprocessor/driver, and/or other discrete electronics. A lead frame may be etched to form a half-etch lead frame defining component attach structures at the top side of the lead frame. A power MOSFET may be mounted to a die attach pad defined in the half-etch lead frame, and the structure may be overmolded. The top of the overmolded structure may be grinded to reduce a thickness of the power MOSFET and expose a top surface of the MOSFET through the surrounding mold compound. A conductive contact may be formed on a top surface of the MOSFET. Selected portions of the half-etch lead frame may be etched from the bottom-up to separate the MOSFET from other package components, and to define a plurality of package posts for solder-mounting the package to a PCB.

Claims (34)

1. A method, comprising:

forming a power integrated circuit (IC) package by a process including:

etching a top side of a lead frame to define a half-etch lead frame defining (a) a plurality of power IC device attach structures and (b) one or more power IC contact attach structures laterally offset from the plurality of power IC device attach structures;

solder mounting a power IC device to the plurality of power IC device attach structures but not to the one or more power IC contact attach structures;

forming a mold compound over the power IC device and half-etch lead frame to define an over-molded structure;

performing a grind process on a top side of the over-molded structure to reduce a thickness of the power IC device and to expose a top surface of the power IC device through the mold compound;

forming a conductive power IC contact extending over and connected to both (a) the power IC device and (b) the one or more power IC contact attach structures;

removing portions of the half-etch lead frame, from a bottom side of the half-etch lead frame, to (a) physically separate the plurality of power IC device attach structures from each other and (b) selectively remove portions of the plurality of power IC device attach structures to define one or more selected power IC device attach structures extending further downward from a bottom side of the power IC package than one or more other power IC device attach structures, wherein the one or more selected power IC device attach structures define one or more package posts extending downwardly from the bottom side of the power IC package; and

plating at least one external surface of each package post to define one or more solder wettable package posts for solder mounting the power IC package.

2. The method of claim 1 , further comprising solder mounting the bottom side of the power IC package to a printed circuit board via the one or more solder wettable package posts.

3. The method of claim 1 , wherein the step of removing portions of the half-etch lead frame, from the bottom side of the half-etch lead frame, defines a plurality of package posts extending from the bottom side of the power IC package; and

the method further comprises:

plating a bottom surface and at least one lateral side surface of each package post to define a plurality of solder wettable package posts; and

solder mounting the power IC package to a printed circuit board via the plurality of solder wettable package posts.

4. The method of claim 1 , wherein the process of forming the power IC package further comprises flip-chip mounting a microcontroller to at least one power IC device attach structure at the top side of the half-etch lead frame.

5. The method of claim 1 , wherein the power IC device comprises a power MOSFET (metal-oxide-semiconductor field-effect transistor).

6. The method of claim 1 , comprising solder mounting a plurality of power IC devices to the plurality of power IC device attach structures.

7. The method of claim 1 , wherein the process of forming the power IC package does not include a Taiko™ thin-grind process.

8. The method of claim 1 , wherein the power IC device is solder mounted to the lead frame without applying a back metal to the power IC device prior to the solder mounting.

9. The method of claim 1 , wherein the one or more solder wettable package posts are configured for through-hole mounting the power IC package through one or more holes formed in a printed circuit board.

10. A method, comprising:

forming a power integrated circuit (IC) package by a process including:

etching a top side of a lead frame to define a half-etch lead frame defining a plurality of power IC device attach structures;

solder mounting a power IC device to at the plurality of power IC device attach structures;

forming a mold compound over the power IC device and half-etch lead frame to define an over-molded structure;

performing a grind process on a top side of the over-molded structure to reduce a thickness of the power IC device and to expose a top surface of the power IC device through the mold compound;

removing a region of remaining mold compound to expose at least one upper surface area of the half-etch lead frame at a location laterally offset from the power IC device;

forming a conductive contact over the power IC device;

forming a discrete supplemental IC device over and electrically connected to the at least one exposed upper surface area of the half-etch lead frame at the location laterally offset from the power IC device, the discrete supplemental IC device being electrically isolated from the power IC device;

removing portions of the half-etch lead frame, from a bottom side of the half-etch lead frame, to (a) physically separate the plurality of power IC device attach structures from each other and (b) selectively remove portions of the plurality of power IC device attach structures to define one or more selected power IC device attach structures extending further downward from a bottom side of the power IC package than one or more other power IC device attach structures, wherein the one or more selected power IC device attach structures define one or more package posts extending downwardly from the bottom side of the power IC package;

plating at least one external surface of each package post to define one or more solder wettable package posts for solder mounting the power IC package.

11. The method of claim 10 , wherein the discrete supplemental IC device comprises a discrete inductor or capacitor.

12. The method of claim 10 , wherein the discrete supplemental IC device comprises an application-specific integrated circuit (ASIC).

13. The method of claim 10 , wherein the one or more solder wettable package posts are configured for through-hole mounting the power IC package through one or more holes formed in a printed circuit board.

Assignments (12)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0335 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059263/0001 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 058214/0625 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 052856/0909 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 8, 2018
From: LAM, MAN KIT
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 046589/0816 →
Continuity (2)
Provisional Application 62655449 · Apr 10, 2018
Related Publication 20190311977A1 · Oct 10, 2019