Constructions comprising stacked memory arrays

1. A method of forming a semiconductor construction, comprising:

forming a first memory array deck comprising phase change memory containing first memory cells comprising a first chalcogenide, the first memory cells being laterally spaced from one another by a first dielectric material;

forming a second memory array deck over the first memory array deck, the second memory array deck containing second memory cells comprising a second chalcogenide that differs from the first chalcogenide in one or both of composition and thickness, the second memory cells being separated from one another by a second dielectric material, the first and second dielectric materials differing from another in one or more structural parameters selected from differing materials and differing material thicknesses; and

providing a first series of access/sense lines and a second series of access/sense lines, the first series of access/sense lines being disposed vertically between the first memory array deck and the second memory array deck, the lines of the first series of access/sense lines being formed of a single material; the second series of access/sense lines being disposed vertically above the second memory array deck, the lines of the second series of access/sense lines comprising multiple materials.

2. The method of claim 1 wherein the first memory array deck has a different access time than the second memory array deck.

3. The method of claim 1 wherein the first memory array deck has a different endurance than the second memory array deck.

4. The method of claim 1 wherein the second memory array deck has faster access times than the first memory array deck; and wherein the first memory array deck has greater endurance than the second memory array deck.

5. The method of claim 1 further comprising forming a series of access/sense lines that are shared between the first and second memory array decks.

6. The method of claim 1 wherein the first memory array deck has durability of at least about 10-fold more cycling times than the second memory array deck.

7. The method of claim 1 wherein the first memory array deck comprises germanium-containing chalcogenide as programmable material of the phase change memory.

8. The method of claim 7 wherein:

the first dielectric material comprises first insulative material liners along sidewalls of the first memory cells;

the second dielectric material comprises second insulative material liners along sidewalls of the second memory cells; and

the first insulative material liners are different thicknesses than the second insulative material liners.

9. The method of claim 1 further comprising forming metallization over the second memory array deck and electrically coupling circuitry of the second memory array deck with circuitry peripheral to the second memory array deck.

10. A method of forming a semiconductor construction, comprising:

forming a first memory array deck;

forming a second memory array deck over the first memory array deck, the second memory array deck differing from the first memory array deck in thicknesses of materials;

wherein the forming the first memory array deck comprises forming first memory cells that are laterally spaced from one another by first dielectric regions along a cross-section;

wherein the forming the second memory array deck comprises forming second memory cells that are laterally spaced from one another by second dielectric regions along the cross-section, the second dielectric regions having a different material thickness than the first dielectric regions; and

forming a first series of access/sense lines disposed vertically between the first memory array deck and the second memory array deck, the lines of the first series of access/sense lines being formed of a single material; and

forming a second series of access/sense lines disposed vertically above the second memory, array deck, the lines of the second series of access/sense lines comprising, multiple materials.

11. The method of claim 10 wherein:

the first memory cells comprise first programmable material;

the second memory cells comprise second programmable material; and

the first programmable material is a different thickness than the second programmable material.

12. The method of claim 10 wherein;

the first memory cells comprise first programmable material;

the second memory cells comprises second programmable material within second memory cells; and

the first programmable material is a different composition than the second programmable material.

13. The method of claim 10 wherein:

the first dielectric regions comprise first insulative material liners along sidewalls of the first memory cells;

the second dielectric regions comprise second insulative material liners along sidewalls of the second memory cells; and

the first insulative material liners are different thicknesses than the second insulative material liners.

14. The method of claim 10 wherein:

the first dielectric regions comprise first insulative material liners along sidewalls of the first memory cells;

the second dielectric regions comprise second insulative material liners along sidewalls of the second memory cells; and

the first insulative material liners are different compositions than the second insulative material liners.

15. The method of claim 10 wherein:

the first dielectric regions comprise first insulative material liners along sidewalls of the first memory cells;

the first dielectric regions comprise a first insulator between the first insulative material liners;

the second dielectric regions comprise second insulative material liners along sidewalls of the second memory cells;

the second dielectric regions comprise a second insulator between the second insulative material liners; and

wherein the second insulator is a different composition relative to the first insulator.

16. The method of claim 10 wherein the first series of access/sense lines are shared between the first and second memory array decks.

17. A method of forming a semiconductor construction, comprising:

forming a first series of access/sense lines extending along a first direction;

forming a second series of access/sense lines over the first series of access/sense lines and extending along a second direction that crosses the first direction;

forming first memory cells between the first and second series of access/sense lines, the first memory cells comprising a first phase change material and being laterally spaced from one another by first dielectric regions along a cross-section;

forming a third set of access/sense lines over the second series of access/sense lines and extending along the first direction; and

forming second memory cells between the second and third series of access/sense lines, the second memory cells comprising a second phase change material and being laterally spaced from one another be second dielectric regions along the cross-section, the second dielectric regions differing from the first dielectric regions by one or more structural parameters selected from differing materials and differing thicknesses of materials; wherein:

the first dielectric regions comprise first insulative material liners along sidewalls of the first memory cells;

the second dielectric regions comprise second insulative material liners along sidewalls of the second memory cells; and

the first insulative material liners are different thicknesses than the second insulative material liners.

18. A method of forming a semiconductor construction, comprising:

forming a first series of access/sense lines extending along a first direction;

forming a second series of access/sense lines over the first series of access/sense lines and extending along a second direction that crosses the first direction;

forming first memory cells between the first and second series of access/sense lines, the first memory cells comprising a first phase change material and being laterally spaced from one another by first dielectric regions along a cross-section;

forming, a third set of access/sense lines over the second series of access/sense lines and extending along the first direction; and

forming second memory cells between the second third series of access/sense lines, the second memory cells comprising a second phase change material and being laterally spaced from one another be second dielectric regions along the cross-section, the second dielectric regions differing from the first dielectric regions by one or more structural parameters selected from differing materials and differing thicknesses of materials; wherein the second series of access/sense lines is formed of a single material and wherein the third series of access/sense lines is formed of multiple materials.

19. The method of claim 18 wherein the single material is a metal and wherein the multiple materials comprises the metal and a low resistance material.