Ferroelectric field effect transistors, pluralities of ferroelectric field effect transistors arrayed in row lines and column lines, and methods of forming a plurality of ferroelectric field effect transistors
A ferroelectric field effect transistor comprises a semiconductive channel comprising opposing sidewalls and an elevationally outermost top. A source/drain region is at opposite ends of the channel. A gate construction of the transistor comprises inner dielectric extending along the channel top and laterally along the channel sidewalk. Inner conductive material is elevationally and laterally outward of the inner dielectric and extends along the channel top and laterally along the channel sidewalk. Outer ferroelectric material is elevationally outward of the inner conductive material and extends along the channel top. Outer conductive material is elevationally outward of the outer ferroelectric material and extends along the channel. Other constructions and methods are disclosed.
1. A memory cell comprising:
a vertically extending semiconductive channel;
first dielectric wrapped over a top surface and a pair of outer sidewalls of the vertically extending channel;
first conductive material wrapped over a top surface and a pair of outer sidewalls of the first dielectric;
ferroelectric material over a top surface of the first conductive material, the ferroelectric material being absent from all outer vertical sidewall surfaces of the first conductive material; and
second conductive material over a top surface of the ferroelectric material; at least one pair of outer sidewalls of the first conductive material, at least one pair of outer sidewalls of the ferroelectric material, and at least one pair of outer sidewalls of the second conductive material being laterally coincident relative one another.
2. The memory cell of claim 1 wherein all of the outer sidewalls of the first conductive material, the ferroelectric material, and the second conductive material are laterally coincident relative one another.
3. A computer comprising multiple memory cells of claim 1 .
4. A system comprising multiple memory cells of claim 1 .
5. A memory cell comprising:
a vertically extending semiconductive channel;
first dielectric wrapped over a top surface and a pair of outer sidewalls of the vertically extending channel;
first conductive material wrapped over a top surface and a pair of outer sidewalls of the first dielectric;
ferroelectric material over a top surface of the first conductive material, the ferroelectric material being absent all outer vertical sidewall surfaces of the first conductive material; and
second conductive material over a top surface of the ferroelectric material; at least one pair of outer sidewalls of the first conductive material and at least one pair of outer sidewalls of the ferroelectric material being laterally coincident relative one another.
6. A computer comprising multiple memory cells of claim 5 .
7. A system comprising multiple memory cells of claim 5 .
8. A memory cell comprising:
a vertically extending semiconductive channel;
first dielectric wrapped over a top surface and a pair of outer sidewalls of the vertically extending channel;
first conductive material wrapped over a top surface and a pair of outer sidewalls of the first dielectric;
ferroelectric material over a top surface of the first conductive material, the ferroelectric material being absent from all outer vertical sidewall surfaces of the first conductive material; and
second conductive material over a top surface of the ferroelectric material; at least one pair of outer sidewalls of the ferroelectric material and at least one pair of outer sidewalls of the second conductive material being laterally coincident relative one another.
9. A computer comprising multiple memory cells of claim 8 .
10. A system comprising multiple memory cells of claim 8 .
11. A memory cell comprising:
a vertically extending semiconductive channel;
first dielectric wrapped over a top surface and a pair of outer sidewalls of the vertically extending channel;
first conductive material wrapped over a top surface and a pair of outer sidewalls of the first dielectric;
ferroelectric material over a top surface of the first conductive material, the ferroelectric material being absent from all outer vertical sidewall surfaces of the first conductive material; and
second conductive material over a top surface of the ferroelectric material; at least one pair of outer sidewalls of the first conductive material and at least one pair of outer sidewalls of the second conductive material being laterally coincident relative one another.
12. A computer comprising multiple memory cells of claim 11 .
13. A system comprising multiple memory cells of claim 11 .