IP Library › Granted Patent US 10,580,492

Granted Patent B2

US 10,580,492 · App. 16/107,282 · Granted Mar 3, 2020

System and method for implementing configurable convoluted neural networks with flash memories

Inventors: Vipin Tiwari (Dublin, CA); Nhan Do (Saratoga, CA)

Assignee: Silicon Storage Technology, Inc.

G11C16/0425 G06N3/061 G06N3/063 G11C16/24 H01L27/11521 H01L27/11524

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Quick Facts

Patent No.: US 10,580,492
App. No.: 16/107,282
Granted: Mar 3, 2020
Kind: B2

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Abstract

A memory array with memory cells arranged in rows and columns. Each memory cell includes source and drain regions with a channel region there between, a floating gate disposed over a first channel region portion, and a second gate disposed over a second channel region portion. A plurality of bit lines each extends along one of the columns and is electrically connected to the drain regions of a first group of one or more of the memory cells in the column and is electrically isolated from the drain regions of a second group of one or more of the memory cells in the column. A plurality of source lines each is electrically connected to the source regions of the memory cells in one of the columns or rows. A plurality of gate lines each is electrically connected to the second gates of memory cells in one of the columns or rows.

Claims (64)

1. A memory array, comprising:

a plurality of memory cells arranged in rows and columns, wherein each of the memory cells includes:

spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between,

a floating gate disposed over and insulated from a first portion of the channel region, and

a second gate disposed over and insulated from a second portion of the channel region;

a plurality of bit lines each extending along a corresponding one of the columns, wherein for each of the bit lines and its corresponding column, the bit line is electrically connected to the drain regions of a first group of one or more of the memory cells in the corresponding column and is electrically isolated from the drain regions of a second group of one or more of the memory cells in the corresponding column;

wherein for each of the columns, the drain regions of the second group of the one or more of the memory cells in the column are not electrically connected to any conductive line extending along the column;

a plurality of source lines each electrically connected to the source regions of at least some of the memory cells in one of the columns or in one of the rows;

a plurality of gate lines each electrically connected to the second gates of at least some of the memory cells in one of the columns or in one of the rows.

2. The memory array of claim 1 , wherein for each of the bit lines and its corresponding column, the memory array further comprises:

a plurality of bit line contacts each electrically connecting the drain region of one of the memory cells in the first group to the bit line.

3. The memory array of claim 2 , wherein for each of the bit lines and its corresponding column, each of the memory cells in the second group lacks a bit line contact electrically connecting the drain region to the bit line.

4. The memory array of claim 1 , wherein for each of the bit lines and its corresponding column, the memory array further comprises:

a plurality of first fuses each electrically connected between the drain region of one of the memory cells in the first group and the bit line, where each of the first fuses is in a conductive state;

a plurality of second fuses each electrically connected between the drain region of one of the memory cells in the second group and the bit line, where each of the second fuses is in a nonconductive state.

5. The memory array of claim 1 , wherein:

a first one of the rows includes a first plurality of the memory cells that are positioned adjacent to each other in a row direction, wherein the drain region for each of the first plurality of memory cells is electrically connected to one of the bit lines;

the first one of the rows includes a second plurality of the memory cells surrounding the first plurality of the memory cells in the row direction, wherein the drain region for each of the second plurality of memory cells is not electrically connected to any of the bit lines;

a second one of the rows is adjacent the first one of the rows and includes a third plurality of the memory cells that are positioned adjacent to each other in the row direction, wherein the drain region for each of the third plurality of memory cells is electrically connected to one of the bit lines;

the second one of the rows includes a fourth plurality of the memory cells surrounding the third plurality of the memory cells in the row direction, wherein the drain region for each of the fourth plurality of memory cells is not electrically connected to any of the bit lines;

wherein one of the first plurality of memory cells and one of the fourth plurality of memory cells are in the same column.

6. The memory array of claim 5 , wherein one of the bit lines is electrically connected to the drain region of one of the first plurality of the memory cells and is not electrically connected to any drain region of the memory cells in the second one of the rows.

7. A memory array, comprising:

a plurality of memory cells arranged in rows and columns, wherein each of the memory cells includes:

spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between,

a floating gate disposed over and insulated from a first portion of the channel region, and

a second gate disposed over and insulated from a second portion of the channel region;

a plurality of source lines each extending along a corresponding one of the rows or columns, wherein for each of the source lines and its corresponding one row or column, the source line is electrically connected to the source regions of a first group of one or more of the memory cells in the corresponding one row or column and is electrically isolated from the source regions of a second group of one or more of the memory cells in the corresponding one row or column;

wherein for each of the corresponding one row or column, the source regions of the second group of the one or more of the memory cells in the corresponding one row or column are not electrically connected to any conductive line extending along the corresponding one row or column;

a plurality of bit lines each electrically connected to the drain regions of at least some of the memory cells in one of the columns;

a plurality of gate lines each electrically connected to the second gates of at least some of the memory cells in one of the columns or in one of the rows.

8. The memory array of claim 7 , wherein for each of the source lines and its corresponding one row or column, the memory array further comprises:

a plurality of source line contacts each electrically connecting the source region of one of the memory cells in the first group to the source line.

9. The memory array of claim 8 , wherein for each of the source lines and its corresponding one row or column, each of the memory cells in the second group lacks a source line contact electrically connecting the source region to the source line.

10. The memory array of claim 7 , wherein for each of the source lines and its corresponding one row or column, the memory array further comprises:

a plurality of first fuses each electrically connected between the source region of one of the memory cells in the first group and the source line, where each of the first fuses is in a conductive state;

a plurality of second fuses each electrically connected between the source region of one of the memory cells in the second group and the source line, where each of the second fuses is in a nonconductive state.

11. The memory array of claim 7 , wherein:

a first one of the rows includes a first plurality of the memory cells that are positioned adjacent to each other in a row direction, wherein the source region for each of the first plurality of memory cells is electrically connected to one of the source lines;

the first one of the rows includes a second plurality of the memory cells surrounding the first plurality of the memory cells in the row direction, wherein the source region for each of the second plurality of memory cells is not electrically connected to any of the source lines;

a second one of the rows is adjacent the first one of the rows and includes a third plurality of the memory cells that are positioned adjacent to each other in the row direction, wherein the source region for each of the third plurality of memory cells is electrically connected to one of the source lines;

the second one of the rows includes a fourth plurality of the memory cells surrounding the third plurality of the memory cells in the row direction, wherein the source region for each of the fourth plurality of memory cells is not electrically connected to any of the source lines;

wherein one of the first plurality of memory cells and one of the fourth plurality of memory cells are in the same column.

12. A memory array, comprising:

a plurality of memory cells arranged in rows and columns, wherein each of the memory cells includes:

spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between,

a floating gate disposed over and insulated from a first portion of the channel region, and

a second gate disposed over and insulated from a second portion of the channel region;

a plurality of gate lines each extending along a corresponding one of the rows or columns, wherein for each of the gate lines and its corresponding one row or column, the gate line is electrically connected to the second gates of a first group of one or more of the memory cells in the corresponding one row or column and is electrically isolated from the second gates of a second group of one or more of the memory cells in the corresponding one row or column;

wherein for each of the corresponding one row or column, the second gates of the second group of the one or more of the memory cells in the corresponding one row or column are not electrically connected to any conductive line extending along the corresponding one row or column;

a plurality of bit lines each electrically connected to the drain regions of at least some of the memory cells in one of the columns;

a plurality of source lines each electrically connected to the source regions of at least some of the memory cells in one of the columns or in one of the rows.

13. The memory array of claim 12 , wherein for each of the gate lines and its corresponding one row or column, the memory array further comprises:

a plurality of gate line contacts each electrically connecting the second gate of one of the memory cells in the first group to the gate line.

14. The memory array of claim 13 , wherein for each of the gate lines and its corresponding one row or column, each of the memory cells in the second group lacks a gate line contact electrically connecting the second gate to the gate line.

15. The memory array of claim 12 , wherein for each of the gate lines and its corresponding one row or column, the memory array further comprises:

a plurality of first fuses each electrically connected between the second gate of one of the memory cells in the first group and the gate line, where each of the first fuses is in a conductive state;

a plurality of second fuses each electrically connected between the second gate of one of the memory cells in the second group and the gate line, where each of the second fuses is in a nonconductive state.

16. The memory array of claim 12 , wherein:

a first one of the rows includes a first plurality of the memory cells that are positioned adjacent to each other in a row direction, wherein the second gate for each of the first plurality of memory cells is electrically connected to one of the gate lines;

the first one of the rows includes a second plurality of the memory cells surrounding the first plurality of the memory cells in the row direction, wherein the second gate for each of the second plurality of memory cells is not electrically connected to any of the gate lines;

a second one of the rows is adjacent the first one of the rows and includes a third plurality of the memory cells that are positioned adjacent to each other in the row direction, wherein the second gate for each of the third plurality of memory cells is electrically connected to one of the gate lines;

the second one of the rows includes a fourth plurality of the memory cells surrounding the third plurality of the memory cells in the row direction, wherein the second gate for each of the fourth plurality of memory cells is not electrically connected to any of the gate lines;

wherein one of the first plurality of memory cells and one of the fourth plurality of memory cells are in the same column.

Assignments (13)

RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022

From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT