Circuit design using high level synthesis and linked hardware description language libraries
Using high level synthesis (HLS) and linked hardware description language (HDL) libraries to implement a circuit design includes generating, using computer hardware, a data flow graph from a model that includes an HDL model block coupled to a non-HDL model block, wherein the HDL model block is derived from HDL code, and dividing, using the computer hardware, the data flow graph into a first sub-graph corresponding to the HDL model block and a second sub-graph corresponding to the non-HDL model block. Using the computer hardware, a first HDL core is generated from the first sub-graph, synthesizable program code is generated form the second sub-graph, HLS is performed on the synthesizable program code to generate a second HDL core, and the circuit design is generated including the first HDL core connected to the second HDL core.
1. A method, comprising:
generating, using computer hardware, a data flow graph from a model that includes a hardware description language (HDL) model block coupled to a non-HDL model block, wherein the HDL model block is derived from HDL code;
dividing, using the computer hardware, the data flow graph into a first sub-graph corresponding to the HDL model block and a second sub-graph corresponding to the non-HDL model block;
generating, using the computer hardware, a first HDL core from the first sub-graph;
generating, using the computer hardware, synthesizable program code from the second sub-graph;
performing, using the computer hardware, high-level synthesis on the synthesizable program code to generate a second HDL core; and
generating, using the computer hardware, a circuit design including the first HDL core connected to the second HDL core.
2. The method of claim 1 , wherein the generating the circuit design comprises:
connecting the first HDL core to the second HDL core.
3. The method of claim 2 , wherein the connecting the first HDL core to the second HDL core comprises:
using external edges of nodes of the first sub-graph and the second sub-graph as port interfaces to connect the first HDL core to the second HDL core.
4. The method of claim 1 , further comprising:
creating the HDL model block from the HDL code, wherein the HDL model block has a model interface derived from an HDL interface of the HDL code.
5. The method of claim 1 , further comprising:
receiving a user-specified parameter for the HDL model block;
wherein the generating the first HDL core includes parameterizing the first HDL core using the parameter.
6. The method of claim 1 , wherein the performing high-level synthesis on the synthesizable program code comprises:
implementing the second HDL core with an HDL interface that matches an HDL interface of the first HDL core.
7. The method of claim 6 , further comprising:
including a hardware compiler directive within the synthesizable program code specifying the HDL interface of the second HDL core.
8. The method of claim 7 , wherein the hardware compiler directive is determined based on a user-specified parameter for the HDL model block.
9. A system, comprising:
a memory configured to store program code; and
a processor coupled to the memory, wherein the processor, in response to executing the program code, is configured to initiate operations including:
generating a data flow graph from a model that includes a hardware description language (HDL) model block coupled to a non-HDL model block, wherein the HDL model block is derived from HDL code;
dividing the data flow graph into a first sub-graph corresponding to the HDL model block and a second sub-graph corresponding to the non-HDL model block;
generating a first HDL core from the first sub-graph;
generating synthesizable program code from the second sub-graph;
performing high-level synthesis on the synthesizable program code to generate a second HDL core; and
generating a circuit design including the first HDL core connected to the second HDL core.
10. The system of claim 9 , wherein the generating the circuit design comprises:
connecting the first HDL core to the second HDL core.
11. The system of claim 10 , wherein the connecting the first HDL core to the second HDL core comprises:
using external edges of nodes of the first sub-graph and the second sub-graph as port interfaces to connect the first HDL core to the second HDL core.
12. The system of claim 9 , wherein the processor is configured to initiate operations further comprising:
creating the HDL model block from the HDL code, wherein the HDL model block has a model interface derived from an HDL interface of the HDL code.
13. The system of claim 9 , wherein the processor is configured to initiate operations further comprising:
receiving a user-specified parameter for the HDL model block;
wherein the generating the first HDL core includes parameterizing the first HDL core using the parameter.
14. The system of claim 9 , wherein the performing high-level synthesis on the synthesizable program code comprises:
implementing the second HDL core with an HDL interface that matches an HDL interface of the first HDL core.
15. The system of claim 14 , wherein the processor is configured to initiate operations further comprising:
including a hardware compiler directive within the synthesizable program code specifying the HDL interface of the second HDL core.
16. The system of claim 15 , wherein the hardware compiler directive is determined based on a user-specified parameter for the HDL model block.
17. A computer program product, comprising:
a computer readable storage medium having program code stored thereon, wherein the program code is executable by computer hardware to initiate operations including:
generating a data flow graph from a model that includes a hardware description language (HDL) model block coupled to a non-HDL model block, wherein the HDL model block is derived from HDL code;
dividing the data flow graph into a first sub-graph corresponding to the HDL model block and a second sub-graph corresponding to the non-HDL model block;
generating a first HDL core from the first sub-graph;
generating synthesizable program code from the second sub-graph;
performing high-level synthesis on the synthesizable program code to generate a second HDL core; and
generating a circuit design including the first HDL core connected to the second HDL core.
18. The computer program product of claim 17 , wherein the program code is executable by the computer hardware to initiate operations including:
receiving a user-specified parameter for the HDL model block;
wherein the generating the first HDL core includes parameterizing the first HDL core using the parameter.
19. The computer program product of claim 17 , wherein the performing high-level synthesis on the synthesizable program code comprises:
implementing the second HDL core with an HDL interface that matches an HDL interface of the first HDL core.
20. The computer program product of claim 19 , wherein the program code is executable by the computer hardware to initiate operations including:
including a hardware compiler directive within the synthesizable program code specifying the HDL interface of the second HDL core.