Granted Patent B2

US 12,730,949 · App. 17/893,156 · Granted Sep 8, 2026

Inventor: Steven F. Hoover (Shrewsbury, MA)

G06F30/323G06F30/3308G06F30/327

Abstract

Claims (35)

1 . A computer-implemented method comprising:

receiving first data representing a hardware-description language (HDL) description of an electronic circuit;

identifying, using the first data, a first description of a first storage element configured to process, during a first time period, an input signal to store data associated with the input signal and to output, during a second time period, an output signal representing the data;

determining a memory structure configured to store the data;

determining a second description of a second storage element configured to store a reference value indicating a location of the data in the computer-memory structure, a topology of the second storage element corresponding to a topology of the first storage element;

determining, using the first data and the second description, a circuit model corresponding to the HDL description and the second storage element;

storing, using a first portion of the circuit model corresponding to the second storage element, the reference value; and

processing, by the memory structure during the second time period, the reference value to output the data.

2 . A computer-implemented method for modeling circuit behavior, the method comprising:

receiving first data representing a hardware-description language (HDL) description of a first electronic circuit;

identifying in the first data, a first representation of a first group of circuit elements corresponding to a circuit-element transformation technique;

determining a second representation of a second group of circuit elements by applying the circuit-element transformation technique to the first group of circuit elements;

identifying a second electronic circuit determined by replacing the first group of circuit elements in the first data with the second group of circuit elements;

simulating operation of the second electronic circuit to determine second data representing values of signals in the second electronic circuit;

determining a first signal corresponding to the first group of circuit elements;

determining a first time period corresponding to a first value of the first signal;

determining, using the circuit-element transformation technique, at least one second signal corresponding to the second group of circuit elements, wherein the second signal, at a second time period, corresponds to a representation of the first value; and

determining using at least one value of the at least one second signal during the second time period and the circuit-element transformation technique, the first value,

wherein the circuit-element transformation technique records a correspondence between the first group of circuit elements and the second group of circuit elements, the correspondence enabling a reverse transform to derive the first value from simulated values of signals of the second electronic circuit.

3 . The computer-implemented method of claim 2 , wherein the circuit-element transformation technique is reversible.

4 . The computer-implemented method of claim 2 , wherein the second group of circuit elements have an equivalent behavior to the first group of circuit elements.

5 . The computer-implemented method of claim 2 , wherein the circuit-element transformation technique corresponds to retiming of operation of at least one data-preserving element.

6 . The computer-implemented method of claim 2 , wherein the circuit-element transformation technique corresponds to migration of logic across at least one data-preserving element.

7 . The computer-implemented method of claim 6 , wherein the at least one data-preserving element comprises:

a multiplexer; and

a flip-flop including:

an input driven by an output of the multiplexer, and

an output connected to an input of the multiplexer.

8 . The computer-implemented method of claim 6 , wherein the data-preserving element comprises an array.

9 . The computer-implemented method of claim 6 , wherein the data-preserving element comprises a queue.

10 . The computer-implemented method of claim 6 , wherein the data-preserving element comprises a ring.

11 . The computer-implemented method of claim 2 , wherein the circuit-element transformation technique comprises time-domain multiplexing.

12 . The computer-implemented method of claim 2 , wherein the circuit-element transformation technique comprises storing data values in a storage array and configures a storage element to refer to a value stored in the storage array.

13 . The computer-implemented method of claim 2 , wherein the circuit-element transformation technique absorbs a storage element into a first-in-first-out (FIFO) component.

14 . The computer-implemented method of claim 2 , wherein the circuit-element transformation technique absorbs a storage element into a queue.

Continuity (3)

References Cited (21)