Memory cell with oxide cap and spacer layer for protecting a floating gate from a source implant
View Patent ↗A method of forming a memory cell, e.g., flash memory cell, may include (a) depositing polysilicon over a substrate, (b) depositing a mask over the polysilicon, (c) etching an opening in the mask to expose a surface of the polysilicon, (d) growing a floating gate oxide at the exposed polysilicon surface, (e) depositing additional oxide above the floating gate oxide, such that the floating gate oxide and additional oxide collectively define an oxide cap, (f) removing mask material adjacent the oxide cap, (g) etching away portions of the polysilicon uncovered by the oxide cap, wherein a remaining portion of the polysilicon defines a floating gate, and (h) depositing a spacer layer over the oxide cap and floating gate. The spacer layer may includes a shielding region aligned over at least one upwardly-pointing tip region of the floating gate, which helps protect such tip region(s) from a subsequent source implant process.
1. A method of forming a memory cell structure, the method comprising:
forming a polysilicon layer over a substrate;
depositing mask material over the polysilicon layer;
etching an opening in the mask material to expose a top surface of the polysilicon layer;
growing a floating gate oxide at the exposed top surface of the polysilicon layer;
depositing additional oxide in the opening in the mask material and above the floating gate oxide, wherein the floating gate oxide and the additional oxide collectively define an oxide cap;
removing mask material adjacent lateral sides of the oxide cap; and
performing a floating gate etch to remove portions of the polysilicon layer uncovered by the oxide cap, wherein a remaining portion of the polysilicon layer defines a floating gate structure including an upwardly-pointing floating gate tip;
depositing a spacer layer over the oxide cap and underlying floating gate structure, wherein the spacer layer includes a shielding region laterally aligned over the upwardly-pointing floating gate tip;
performing a source implant for forming a source region in the substrate, wherein the shielding region of the spacer layer shields the underlying floating gate tip from the source implant; and
after the source implant, forming an erase gate or coupling gate over the source region and adjacent the upwardly-pointing floating gate tip.
2. The method of claim 1 , wherein the oxide cap is formed with a flat top surface.
3. The method of claim 1 , comprising performing a chemical mechanical planarization (CMP) on the additional oxide to define a flat top surface of the oxide cap.
4. The method of claim 1 , wherein the spacer layer comprises silicon nitride.
5. The method of claim 1 , wherein the shielding region of the spacer layer extends vertically.
6. The method of claim 5 , wherein a vertical height of the vertically-extending shielding region of the spacer layer is greater than a lateral width of the shielding region.
7. The method of claim 6 , wherein the vertical height of the vertically-extending shielding region of the spacer layer is at least two times as great as the lateral width of the shielding region.
8. The method of claim 6 , wherein the vertical height of the vertically-extending shielding region of the spacer layer is at least three times as great as the lateral width of the shielding region.
9. A method of forming a memory cell structure, the method comprising:
forming a polysilicon layer over a substrate;
depositing mask material over the polysilicon layer;
etching a pair of openings in the mask material to expose a pair of top surface regions of the polysilicon layer;
growing a floating gate oxide at each exposed top surface region of the polysilicon layer;
depositing additional oxide in each of the pair of openings in the mask material and above each respective floating gate oxide, wherein each floating gate oxide and the additional oxide deposited over that floating gate oxide collectively defines an oxide cap;
removing mask material adjacent lateral sides of each oxide cap; and
performing a floating gate etch to remove portions of the polysilicon layer uncovered by each oxide cap, wherein remaining portions of the polysilicon layer define a pair of spaced apart floating gate structures, each including an upwardly-pointing floating gate tip;
depositing a spacer layer including a shielding region laterally aligned over the upwardly-pointing floating gate tip of each floating gate structure;
performing a source implant between the pair of floating gate structures, wherein the shielding region of the spacer layer aligned over each upwardly-pointing floating gate tip shields the underlying floating gate tip from the source implant; and
after the source implant, forming an erase gate or coupling gate over the source region and adjacent the upwardly-pointing floating gate tips of the pair of floating gate structures.
10. The method of claim 9 , wherein each oxide cap is formed with a flat top surface.
11. A method of forming a memory cell structure, comprising:
forming a floating gate over a substrate; and
forming an oxide cap over the floating gate by:
growing an oval shaped oxide region at a top surface of the floating gate, wherein the growing the oval shaped oxide region defines first and second upwardly-pointing tip regions of the floating gate at opposing lateral sides of the floating gate; and
depositing an upper oxide region on top of the oval shaped oxide region;
wherein the deposited upper oxide region has a smaller lateral width than the underlying floating gate at each of the opposing lateral sides of the floating gate such that at each of the opposing lateral sides of the floating gate, a vertically-extending sidewall of the upper oxide region is offset from a vertically-extending sidewall of the underlying floating gate in a direction toward a center of the floating gate.
12. The method of claim 11 , wherein the upper oxide region of the oxide cap has a flat top surface.
13. The method of claim 11 , further comprising forming a spacer layer over the oxide cap and underlying floating gate, wherein the spacer layer includes a shielding region laterally aligned over an upwardly-pointing tip region of the floating gate, the shielding region being configured to protect the floating gate tip region during a dopant implant process.
14. The method of claim 11 , further comprising:
forming a spacer layer over the oxide cap and underlying floating gate, wherein the spacer layer includes a shielding region laterally aligned over each of the first and second upwardly-pointing floating gate tip regions and configured to protect the first and second upwardly-pointing floating gate tip regions during a dopant implant process;
forming a wordline adjacent the first upwardly-pointing floating gate tip region, the wordline configured for read or write operations through the first upwardly-pointing floating gate tip region and the wordline; and
forming an erase gate adjacent the second upwardly-pointing floating gate tip region, the erase gate configured for erase operations through the second upwardly-pointing floating gate tip region and the erase gate.