IP Library Granted Patent US 11,088,187
Granted Patent B2
US 11,088,187 · App. 16/114,871 · Granted Aug 10, 2021

Solid-state imaging device and method for manufacturing solid-state imaging device, and electronic device

Inventors: Keiji Tatani (Kumamoto, JP); Fumihiko Koga (Kanagawa, JP); Takashi Nagano (Kanagawa, JP)
H01L27/14612H01L27/1463H01L27/14603H01L27/14607H01L27/14609H01L27/14636H01L27/14641H01L27/14643H01L27/14689
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Quick Facts
Patent No.
US 11,088,187
App. No.
16/114,871
Granted
Aug 10, 2021
Kind
B2
Abstract

A solid-state imaging device includes a first-conductivity-type semiconductor well region, a plurality of pixels each of which is formed on the semiconductor well region and is composed of a photoelectric conversion portion and a pixel transistor, an element isolation region provided between the pixels and in the pixels, and an element isolation region being free from an insulation film and being provided between desired pixel transistors.

Claims (37)

1. An imaging device, comprising:

a first area including a first set of photodiodes that share a first floating diffusion region arranged in the first area and a second set of photodiodes that share a second floating diffusion region arranged in the first area, wherein the first set of photodiodes and the second set of photodiodes are arranged along a first direction;

a second area including a first portion, a second portion, and a third portion arranged between the first and second portions along the first direction, the first portion including a first set of transistors that include a first amplification transistor coupled to the first floating diffusion region, the second portion including a second set of transistors that include a second amplification transistor coupled to the second floating diffusion region, the third portion including a well contact region and a portion of an element isolation region, wherein the first area and the second area are arranged along a second direction perpendicular to the first direction, wherein the well contact region is configured to apply a voltage to a semiconductor well region;

a first reset transistor coupled to the first floating diffusion region;

a second reset transistor coupled to the second floating diffusion region;

at least one first transfer transistor coupled to the first floating diffusion region; and

at least one second transfer transistor coupled to the second floating diffusion region.

2. The imaging device of claim 1 , wherein the element isolation region in the second area includes an impurity diffusion region.

3. The imaging device of claim 2 , wherein the well contact region is coupled to the impurity diffusion region in the element isolation region.

4. The imaging device of claim 1 , wherein the second area further includes a first selection transistor coupled to the first amplification transistor and a second selection transistor coupled to the second amplification transistor.

5. The imaging device of claim 1 , further comprising a plurality of first areas arranged alternating with a plurality of second areas along the second direction.

6. The imaging device of claim 1 , wherein each of the first area and the second area extends along the first direction.

7. The imaging device of claim 1 , wherein

the first set of photodiodes includes a first photodiode and a second photodiode,

the at least one first transfer transistor comprises a first transfer transistor coupled to the first photodiode and the first floating diffusion region, and a second transfer transistor coupled to the second photodiode and the first floating diffusion region,

the second set of photodiodes includes a third photodiode and a fourth photodiode, and

the at least one second transfer transistor comprises a third transfer transistor coupled to the third photodiode and the second floating diffusion region, and a fourth transfer transistor coupled to the fourth photodiode and the second floating diffusion region.

8. An imaging device comprising:

a first set of photodiodes that share a first floating diffusion region in a first area;

a first set of transistors that include a first amplification transistor, a first reset transistor, and at least one first transfer transistor coupled to the first floating diffusion region;

a second set of photodiodes that share a second floating diffusion region in the first area, wherein the first set of photodiodes and the second set of photodiodes are arranged along a first direction;

a second set of transistors that include a second amplification transistor, a second reset transistor, and at least one second transfer transistor coupled to the second floating diffusion region;

an element isolation region; and

a well contact region configured to apply a voltage to a semiconductor well region,

wherein the first set of photodiodes and the first set of transistors are arranged along a second direction perpendicular to the first direction,

wherein the first set of transistors is located in a first portion of a second area, the second set of transistors is located in a second portion of the second area, and a third portion of the second area arranged between the first portion and the second portion along the first direction includes the well contact region and a portion of the element isolation region, and

wherein the first area and the second area are arranged along a second direction perpendicular to the first direction.

9. The imaging device of claim 8 , wherein the element isolation region includes an impurity diffusion region.

10. The imaging device of claim 9 , wherein the well contact region is coupled to the impurity diffusion region in the element isolation region.

11. The imaging device of claim 8 , further comprising:

a first selection transistor coupled to the first amplification transistor; and

a second selection transistor coupled to the second amplification transistor.

12. The imaging device of claim 8 , wherein

the first set of photodiodes includes a first photodiode and a second photodiode,

the at least one first transfer transistor comprises a first transfer transistor coupled to the first photodiode and the first floating diffusion region, and a second transfer transistor coupled to the second photodiode and the first floating diffusion region,

the second set of photodiodes includes a third photodiode and a fourth photodiode, and

the at least one second transfer transistor comprises a third transfer transistor coupled to the third photodiode and the second floating diffusion region, and a fourth transfer transistor coupled to the fourth photodiode and the second floating diffusion region.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 24, 2018
From: TATANI, KEIJI; KOGA, FUMIHIKO; NAGANO, TAKASHI
To: SONY CORPORATION
Reel/Frame 047129/0565 →
Priority Claims (1)
JP 2009-221387 · Sep 25, 2009 · national
Continuity (5)
Continuation 15337291 · Oct 28, 2016
Continuation 14963113 · Dec 8, 2015
Continuation 14487699 · Sep 16, 2014
Continuation 12881643 · Sep 14, 2010
Related Publication 20180366502A1 · Dec 20, 2018
Cited By (1)
US 12,587,753