One-transistor dram cell device based on polycrystalline silicon with FinFET structure and fabrication method thereof
The present invention provides a polysilicon-based 1T DRAM cell device having a FinFET structure and its fabrication method. In the present invention, a semiconductor layer (for example, a polysilicon layer) having a relatively low crystallinity is intentionally formed on the upper layer of the active fin to physically trap the holes accumulated in the conventional cell body, thereby remarkably improving the retention time. A polysilicon-based 1T DRAM cell device having a FinFET structure can also increase the operating efficiency by raising the gate's channel control force and implement the batch process with the functional blocks in the CPU that already have the FinFET structure.
1. A 1T DRAM cell device comprising:
a blocking insulating layer;
a first semiconductor layer having a fin shape protruded on the blocking insulating layer; source and drain regions spaced apart by a channel region in the first semiconductor layer and having a conductivity type opposite to that of the channel region;
a second semiconductor layer formed along the fin shape on the channel region; and
a gate insulating film and a gate surrounding the channel region and the second semiconductor layer in a direction crossing the fin shape on the blocking insulating layer,
wherein the second semiconductor layer is a semiconductor material layer having a crystallinity equal to or lower than that of the first semiconductor layer.
2. The 1T DRAM cell device of claim 1 , wherein the semiconductor material layer is a silicon-based material layer.
3. The 1T DRAM cell device of claim 2 , where the blocking insulating layer is a silicon oxide film formed on a silicon substrate or a buried oxide film (BOX) of an SOI (Silicon-On-Insulator) substrate, where the channel region is doped with impurities such that a band-to-band tunneling occurs in the drain region when a write voltage is applied to the gate, and where the second semiconductor layer is a hole trapping layer that captures holes with a grain boundary.
4. The 1T DRAM cell device of claim 3 , wherein the first semiconductor layer is a single crystal silicon, and wherein the second semiconductor layer is polysilicon.
5. The 1T DRAM cell device of claim 1 , where the blocking insulating layer is a silicon oxide film formed on a silicon substrate or a buried oxide film (BOX) of an SOI (Silicon-On-Insulator) substrate, where the channel region is doped with impurities such that a band-to-band tunneling occurs in the drain region when a write voltage is applied to the gate, and where the second semiconductor layer is a hole trapping layer that captures holes with a grain boundary.
6. The 1T DRAM cell device of claim 5 , wherein the first semiconductor layer is a single crystal silicon, and wherein the second semiconductor layer is polysilicon.
7. A 1T DRAM cell device comprising:
a blocking insulating layer;
a first semiconductor layer having a fin shape protruded on the blocking insulating layer; source and drain regions spaced apart by a channel region in the first semiconductor layer and having a conductivity type opposite to that of the channel region;
a second semiconductor layer formed along the fin shape on the channel region; and
a gate insulating film and a gate surrounding the channel region and the second semiconductor layer in a direction crossing the fin shape on the blocking insulating layer,
where the blocking insulating layer is a silicon oxide film formed on a silicon substrate or a buried oxide film (BOX) of an SOI (Silicon-On-Insulator) substrate, where the channel region is doped with impurities such that a band-to-band tunneling occurs in the drain region when a write voltage is applied to the gate, and where the second semiconductor layer is a hole trapping layer that captures holes with a grain boundary, and
wherein the first semiconductor layer is a single crystal silicon, and wherein the second semiconductor layer is polysilicon.