IP Library Granted Patent US 10,748,938
Granted Patent B2
US 10,748,938 · App. 16/134,201 · Granted Aug 18, 2020

Array substrate, method of manufacturing the same and display device

Inventors: Tianmin Zhou (Beijing, CN); Wei Yang (Beijing, CN); Lizhong Wang (Beijing, CN); Jipeng Song (Beijing, CN)
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
H01L27/1225H01L27/127H01L27/1222H01L27/1248H01L27/1251H01L27/1262H01L27/1296H01L21/3003H01L29/7869H01L29/78609H01L29/78675
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Quick Facts
Patent No.
US 10,748,938
App. No.
16/134,201
Granted
Aug 18, 2020
Kind
B2
Abstract

an array substrate, a method of manufacturing the array substrate, and a display device are provided. The array substrate includes: a base substrate; a first thin film transistor and a second thin film transistor on the base substrate, wherein the first thin film transistor comprises a first active layer, the second thin film transistor comprises a second active layer, and the second active layer is on a side of the first active layer away from the base substrate; and an interlayer dielectric layer and a first buffer layer between the first active layer and the second active layer, wherein the interlayer dielectric layer is capable of supplying hydrogen and the first buffer layer is capable of blocking hydrogen.

Claims (15)

1. An array substrate, comprising:

a base substrate;

a first thin film transistor and a second thin film transistor on the base substrate, wherein the first thin film transistor comprises a first active layer, the second thin film transistor comprises a second active layer, and the second active layer is on a side of the first active layer away from the base substrate; and

an interlayer dielectric layer and a first buffer layer between the first active layer and the second active layer, wherein the interlayer dielectric layer is capable of supplying hydrogen and the first buffer layer is capable of blocking hydrogen,

wherein the first thin film transistor comprises a first gate electrode, the second thin film transistor comprises a second gate electrode, and the first gate electrode and the second gate electrode are in the same layer and both between the first active layer and the interlayer dielectric layer.

2. The array substrate according to claim 1 , wherein the first active layer is a polysilicon active layer, the second active layer is an oxide semiconductor active layer, and the first buffer layer is on a side of the interlayer dielectric layer away from the base substrate.

3. The array substrate according to claim 2 , further comprising a second buffer layer capable of supplying oxygen, the second buffer layer being between the first buffer layer and the oxide semiconductor active layer.

4. The array substrate according to claim 1 , wherein the first thin film transistor comprises a first source electrode and a first drain electrode, and the second thin film transistor comprises a second source electrode and a second drain electrode, one of the first source electrode and the first drain electrode is electrically connected to one of the second source electrode and the second drain electrode.

5. The array substrate according to claim 4 , wherein the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are all in the same layer and between the interlayer dielectric layer and the first buffer layer.

6. The array substrate according to claim 5 , wherein the one of the first source electrode and the first drain electrode and the one of the second source electrode and the second drain electrode constitute a single unitary electrode.

7. The array substrate according to claim 1 , wherein material of the first buffer layer comprises aluminum oxide, silicon nitride or organic material.

8. The array substrate according to claim 3 , wherein material of the second buffer layer comprises silicon oxide.

9. The array substrate according to claim 3 , wherein the first buffer layer has an oxygen content smaller than that of the second buffer layer, and the first buffer layer has a hydrogen content greater than that of the second buffer layer.

10. The array substrate according to claim 2 , further comprising a gate insulating layer between the polysilicon active layer and a gate electrode layer comprising the first gate electrode and the second gate electrode.

11. A display device comprising the array substrate according to claim 1 .

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 18, 2018
From: ZHOU, TIANMIN; YANG, WEI; WANG, LIZHONG; SONG, JIPENG
To: BOE TECHNOLOGY GROUP CO., LTD.
Reel/Frame 046899/0718 →
Priority Claims (1)
CN 2017 1 0867028 · Sep 22, 2017 · national
Continuity (1)
Related Publication 20190096920A1 · Mar 28, 2019
Cited By (2)
US 12,289,957 US 12,432,980