Five-level switched-capacitance DAC using bootstrapped switches
View Patent ↗A charge transfer digital-to-analog converter includes a differential reference voltage, a pair of capacitors, and switches including a shorting switch. The switches are configured to be switched in successive phases to generate a charge transfer through the capacitors to generate an output corresponding to a digital input. The specific switches activated and deactivated in each phase are selected according to the digital input. Each capacitor of the pair of capacitors is connected to a respective pin for the output. The shorting switch is configured to short the pair of capacitors to create a zero-differential charge on a first side of the capacitors. The shorting switch is implemented with a bootstrap circuit to maintain a constant common mode voltage of the first side of the capacitors while the shorting switch is activated.
1. An apparatus, comprising:
a charge transfer digital-to-analog converter (DAC), the DAC comprising:
a differential reference voltage;
a pair of capacitors;
a plurality of switches including a shorting switch; and
wherein:
the plurality of switches are configured to be switched in successive phases to generate a charge transfer through the capacitors to generate an output corresponding to a digital input, wherein the specific switches activated and deactivated in each phase are selected according to the digital input;
each capacitor of the pair of capacitors is connected to a respective pin for the output;
the shorting switch is configured to short the pair of capacitors to create a zero-differential charge on a first side of the capacitors; and
the shorting switch is implemented with a bootstrap circuit to maintain a constant common mode voltage of the first side of the capacitors while the shorting switch is activated.
2. The apparatus of claim 1 , further comprising a voltage follower circuit configured to provide input into the shorting switch.
3. The apparatus of claim 2 , wherein the voltage follower circuit is configured to receive as an input a midpoint voltage of the differential reference voltage.
4. The apparatus of claim 2 , wherein the voltage follower circuit is configured to generate a follow voltage that matches the common mode voltage of the pair of capacitors.
5. The apparatus of claim 2 , wherein the voltage follower circuit is configured to provide sufficient current to bias a transistor of the shorting switch.
6. The apparatus of claim 2 , wherein the voltage follower circuit is a wire connecting the shorting switch with a midpoint of a voltage divider for the differential reference voltage.
7. The apparatus of claim 1 , wherein during a startup phase, a midpoint voltage of the differential reference voltage is applied to each of the pair of capacitors to define the common mode voltage.
8. The apparatus of claim 1 , wherein during a startup phase, differential nodes of the differential reference voltage are applied to the pair of capacitors to define the common mode voltage.
9. The apparatus of claim 1 , wherein:
the shorting switch includes a transistor configured to control a connection between an input pin and an output pin, the input pin and the output pin connected to respective ones of the pair of capacitors;
the input pin and the output pin are isolated from the bootstrap circuit.
10. The apparatus of claim 8 , wherein the bootstrap circuit is configured to control a gate of the transistor to control the connection between the input pin and the output pin.
11. The apparatus of claim 1 , wherein:
the apparatus further includes a voltage follower circuit configured to provide input into the shorting switch;
the shorting switch includes a transistor configured to control a connection between respective ones of the pair of capacitors; and
the input from the voltage follower circuit into the shorting switch is configured to be input into the bootstrap circuit and to be isolated from the output.
12. The apparatus of claim 1 :
wherein the shorting switch includes a transistor configured to control a connection between an input pin and an output pin, the input pin and the output pin connected to respective ones of the pair of capacitors; and
further comprising reset switches connecting a midpoint of the differential reference voltage and the input pin and the output pin, wherein the reset switches are configured to be engaged to equalize voltages of the input pin and the output pin to the midpoint of the differential reference voltage during a reset phase.
13. The apparatus of claim 1 , wherein the shorting switch is configured to maintain symmetry of differential inputs on the first side of the capacitors.
14. The apparatus of claim 13 , wherein the symmetry is defined by a same impedance seen at each first side of the capacitors so that a differential charge remains constant during switching of the capacitors when the shorting switch is enabled.
15. A method, comprising:
switching a plurality of switches, the switches including a shorting switch, of a DAC in successive phases to generate a charge transfer through a pair of capacitors of the DAC to generate an output corresponding to a digital input;
selecting switches to activate and deactivate in the successive phases according to the digital input;
connecting each of the pair of capacitors to a respective pin for the output;
shorting, with the shorting switch, the pair of capacitors to create a zero-differential charge on a first side of the capacitors;
within a bootstrap circuit of the shorting switch, maintaining a constant common mode voltage of the first side of the capacitors while the shorting switch is activated; and
providing input into the shorting switch from a voltage follower circuit, the input a midpoint voltage of a differential reference voltage that is a follow voltage that matches the common mode voltage of the pair of capacitors and is configured to provide sufficient current to bias a transistor of the shorting switch.
16. The method of claim 15 , wherein during a startup phase, the midpoint voltage of the differential reference voltage is applied to each of the pair of capacitors to define the common mode voltage.
17. The method of claim 15 , wherein during a startup phase, differential nodes of the differential reference voltage are applied to the pair of capacitors to define the common mode voltage.
18. The method of claim 15 , further comprising isolating an input pin and an output pin connected to the shorting switch from the bootstrap circuit.
19. The method of claim 15 , further comprising maintaining symmetry of differential inputs on the first side of the capacitors wherein the symmetry is defined by a same impedance seen at each first side of the capacitors so that a differential charge remains constant during switching of the capacitors when the shorting switch is enabled.
20. The method of claim 15 , further comprising equalizing voltages, the voltages of an input pin and an output pin connected to the shorting switch, to a midpoint of a differential reference voltage during a reset phase with reset switches.