Three-dimensional flat NAND memory device including wavy word lines and method of making the same

1. A three-dimensional memory device, comprising:

alternating stacks of insulating strips and electrically conductive strips located over a substrate, generally extending along a first horizontal direction, and laterally spaced apart from each other along a second horizontal direction by width-modulated line trenches, wherein each of the width-modulated line trenches comprises a respective pair of sidewalls defined by surfaces of a respective pair of alternating stacks and includes a laterally alternating sequence of laterally-concave and vertically-planar sidewall segments and laterally-convex and vertically-planar sidewall segments;

memory films located on a respective sidewall of the alternating stacks, generally extending along the first horizontal direction, and laterally undulating along the second horizontal direction; and

a plurality of discrete vertical semiconductor channels located on first portions of a sidewall of a respective one of the memory films that contact the laterally-convex and vertically-planar sidewall segments of the width-modulated line trenches, wherein gaps between neighboring pairs of vertical semiconductor channels are present adjacent to second portions of the memory films that are located on the laterally-concave and vertically-planar sidewall segments of the width-modulated line trenches;

wherein each of the memory films includes a respective layer stack that comprises a blocking dielectric that contacts a respective one of the alternating stacks, a charge storage layer contacting the blocking dielectric, and a tunneling dielectric contacting the charge storage layer and a row of vertical semiconductor channels located within a respective width-modulated line trench.

2. The three-dimensional memory device of claim 1 , wherein:

each of plurality of discrete vertical semiconductor channels includes a respective laterally-concave and vertically-planar outer sidewall that contacts a laterally-convex and vertically-planar sidewall of the respective one of the memory films; and

each of the width-modulated line trenches has the pair of sidewalls that generally extend along the first horizontal direction.

3. The three-dimensional memory device of claim 1 , wherein:

each of the width-modulated line trenches includes a periodic laterally alternating sequence of a neck region and a bulbous region having a greater width than a width of the neck region; and

each of the discrete vertical semiconductor channels is located in one of the neck regions.

4. The three-dimensional memory device of claim 3 , wherein a neck regions of a first width-modulated line trench within each neighboring pair of the width-modulated line trenches is laterally offset along the first horizontal direction from a neck region of a second width-modulated line trench within each neighboring pair of the width-modulated line trenches by a lateral offset distance that is one half of a periodicity of neck regions of the first width-modulated line trench along the first horizontal direction.

5. The three-dimensional memory device of claim 3 , wherein:

each of the vertical semiconductor channels includes a respective laterally-convex and vertically-planar inner sidewall that contacts a respective dielectric core; and

each memory film continuously extends through the neck regions and the bulbous regions of a respective one of the width-modulated line trenches.

6. The three-dimensional memory device of claim 5 , further comprising a two-dimensional array of dielectric pillar structures located within the bulbous regions of the width-modulated line trenches.

7. The three-dimensional memory device of claim 6 , wherein each of the dielectric pillar structures includes a pair of first laterally-convex and vertically-planar sidewalls that contact a respective pair of memory films.

8. The three-dimensional memory device of claim 7 , wherein each of the dielectric pillar structures includes a pair of second laterally-convex and vertically-planar sidewalls that contact a respective pair of dielectric cores.

9. The three-dimensional memory device of claim 6 , wherein:

each of the width-modulated line trenches includes a laterally alternating sequence of the dielectric cores comprising a first dielectric material and the dielectric pillar structures comprising a second dielectric material; and

each interface between a neighboring pair of a dielectric core and a dielectric pillar structure includes a surface at which a laterally convex-sidewall of the dielectric pillar structure contacts a laterally-concave sidewall of the dielectric core.

10. The three-dimensional memory device of claim 9 , wherein:

the first dielectric material comprises a material selected from doped silicate glass, undoped silicate glass, or organosilicate glass; and

the second dielectric material comprises a material selected from undoped silicate glass, doped silicate glass, or organosilicate glass.

11. The three-dimensional memory device of claim 9 , wherein each of the dielectric pillar structures includes a pair of first laterally-convex and vertically-planar sidewalls that contact a respective pair of memory films located within a respective one of the width-modulated line trenches.

12. The three-dimensional memory device of claim 1 , wherein the insulating strips and the electrically conductive strips have a substantially uniform width in the second horizontal direction.

13. The three-dimensional memory device of claim 1 , further comprising:

a contact region in which each of the alternating stacks has respective stepped surfaces that extend from the substrate to a topmost electrically conductive strip within a respective alternating stack; and

a two-dimensional array of contact via structures contacting a top surface of a respective one of the electrically conductive strips within the alternating stacks in the contact region.

14. The three-dimensional memory device of claim 1 , wherein:

each of the width-modulated line trenches includes a periodic laterally alternating sequence of a neck region and a bulbous region having a greater width than a width of the neck region;

dielectric cores comprising a first dielectric material are located within the bulbous regions of the width-modulated line trenches; and

dielectric pillar structures comprising a second dielectric material are located within the bulbous regions of the width-modulated line trenches having a greater lateral dimension along a widthwise direction of the width-modulated line trenches than a maximum lateral dimension of each of the dielectric cores along the widthwise direction of the width-modulated line trenches.

15. The three-dimensional memory device of claim 14 , wherein:

each of the width-modulated line trenches includes a respective laterally alternating sequence of dielectric cores and dielectric pillar structures; and

each interface between a neighboring pair of a dielectric core and a dielectric pillar structure within each of the width-modulated line trenches includes a surface at which a laterally convex-sidewall of the dielectric pillar structure contacts a laterally-concave sidewall of the dielectric core.

16. The three-dimensional memory device of claim 14 , wherein one of the dielectric pillar structures is in direct contact with:

sidewall of four vertical semiconductor channels among the vertical semiconductor channels;

sidewalls of two dielectric cores among the dielectric cores; and

sidewalls of two memory films among the memory films.

17. The three-dimensional memory device of claim 1 , wherein each of the vertical semiconductor channels comprises a respective laterally-concave and vertically-planar outer sidewall contacting a laterally-convex and vertically-planar sidewall of a respective first portion of the memory films.

18. The three-dimensional memory device of claim 17 , further comprising a two-dimensional array of dielectric cores located within the width-modulated line trenches, wherein each dielectric core within the array of dielectric cores comprise a respective pair of laterally-concave and vertically planar sidewalls.

19. The three-dimensional memory device of claim 18 , wherein each laterally-concave and vertically planar sidewall is in contact with a respective laterally-convex and vertically-planar outer sidewall of one of the vertical semiconductor channels.