Three-dimensional memory device with backside support pillar structures and methods of forming the same
A three-dimensional memory device includes alternating stacks of insulating layers and electrically conductive layers. The alternating stacks are laterally spaced apart among one another by backside isolation assemblies. At least one of the backside isolation assemblies generally extends along a first horizontal direction with lateral undulations along a second horizontal direction that is perpendicular to the first horizontal direction. At least one of the alternating stacks has a modulation in width along the second horizontal direction as a function of a position along the first horizontal direction. Memory stack structures vertically extend through a respective one of the alternating stacks. Each of the backside isolation assemblies includes a respective laterally alternating sequence of backside dielectric isolation walls and backside dielectric support pillar structures.
1 . A three-dimensional memory device, comprising:
alternating stacks of insulating layers and electrically conductive layers, wherein the alternating stacks are laterally spaced apart from each other by backside isolation assemblies that generally laterally extend along a first horizontal direction through entire heights of the alternating stacks with lateral undulations along a second horizontal direction that is perpendicular to the first horizontal direction, and wherein each of the alternating stacks has a modulation in width along the second horizontal direction as a function of a position along the first horizontal direction; and
memory stack structures that vertically extend through a respective one of the alternating stacks, and wherein each of the memory stack structures comprises a respective vertical semiconductor channel and a respective vertical stack of memory elements,
wherein each of the backside isolation assemblies comprises a respective laterally alternating sequence of backside dielectric isolation walls and dielectric support pillar structures such that a subset of the dielectric support pillar structures is in direct contact with a respective pair of backside dielectric isolation walls of the backside dielectric isolation walls; and
wherein at least one of the dielectric support pillar structures has a respective pair of lateral indentations that is filled by end portions of a respective pair of backside dielectric isolation walls of the backside dielectric isolation walls.
2 . The three-dimensional memory device of claim 1 , wherein a subset of the backside dielectric isolation walls laterally extends along a horizontal direction that is not parallel to, and is not perpendicular to, the first horizontal direction.
3 . The three-dimensional memory device of claim 1 , wherein:
a first subset of the memory stack structures is located in a first memory array region in a plan view;
a second subset of the memory stack structures is located in a second memory array region that is laterally spaced from the first memory array region in the plan view; and
the modulation in width in each of the alternating stacks is present within an inter-array region that is located between the first memory array region and the second memory array region.
4 . The three-dimensional memory device of claim 3 , wherein each of the alternating stacks has a uniform width along the second horizontal direction in each of the first memory array region and the second memory array region.
5 . The three-dimensional memory device of claim 4 , wherein each of the alternating stacks has a respective first portion having a greater width along the second horizontal direction than the uniform width and a respective second portion having a lesser width along the second horizontal direction than the uniform width in the inter-array region.
6 . The three-dimensional memory device of claim 4 , wherein each of the alternating stacks embeds a respective retro-stepped dielectric material portion therein.
7 . The three-dimensional memory device of claim 6 , wherein each of the retro-stepped dielectric material portions is in contact with a respective one of the backside isolation assemblies and does not contact any other of the backside isolation assemblies.
8 . The three-dimensional memory device of claim 6 , wherein each of the retro-stepped dielectric material portions is not in contact with any of the backside isolation assemblies.
9 . The three-dimensional memory device of claim 6 , wherein one of the backside isolation assemblies is in contact with a pair of retro-stepped dielectric material portions that are laterally spaced from each other along the second horizontal direction and having a same lateral extent along the first horizontal direction.
10 . The three-dimensional memory device of claim 9 , wherein the pair of retro-stepped dielectric material portions comprises a first retro-stepped dielectric material portion having a first lengthwise sidewall that laterally extends along the first horizontal direction and not contacting said one of the backside isolation assemblies, and a second retro-stepped dielectric material portion having a second lengthwise sidewall that laterally extends along the first horizontal direction and not contacting said one of the backside isolation assemblies.
11 . The three-dimensional memory device of claim 10 , wherein a first lateral spacing between a top edge of the first lengthwise sidewall and said one of the backside isolation assemblies is different from a second lateral spacing between a top edge of the second lengthwise sidewall and said one of the backside isolation assemblies.
12 . The three-dimensional memory device of claim 6 , wherein each of the retro-stepped dielectric material portions has a width along the second horizontal direction that is greater than the uniform width.
13 . The three-dimensional memory device of claim 6 , further comprising layer contact via structures vertically extending through a respective one of the retro-stepped dielectric material portions and contacting a top surface of a respective one of the electrically conductive layers.
14 . The three-dimensional memory device of claim 6 , further comprising field dielectric support pillar structures located in the inter-array region, not contacting the backside isolation assemblies, and having a same material composition and a same height as the dielectric support pillar structures.
15 . The three-dimensional memory device of claim 1 , wherein each neighboring pair of alternating stacks of the alternating stacks is laterally spaced from each other by a respective one of backside isolation assemblies, and is not in direct contact with each other.
16 . A three-dimensional memory device, comprising:
alternating stacks of insulating layers and electrically conductive layers, wherein the alternating stacks are laterally spaced apart from each other by backside isolation assemblies that generally laterally extend along a first horizontal direction through entire heights of the alternating stacks with lateral undulations along a second horizontal direction that is perpendicular to the first horizontal direction, and wherein each of the alternating stacks has a modulation in width along the second horizontal direction as a function of a position along the first horizontal direction; and
memory stack structures that vertically extend through a respective one of the alternating stacks, and wherein each of the memory stack structures comprises a respective vertical semiconductor channel and a respective vertical stack of memory elements,
wherein:
each of the backside isolation assemblies comprises a respective laterally alternating sequence of backside dielectric isolation walls and dielectric support pillar structures such that a subset of the dielectric support pillar structures is in direct contact with a respective pair of backside dielectric isolation walls of the backside dielectric isolation walls;
wherein at least one of the dielectric support pillar structures has a respective pair of lateral indentations that is filled by end portions of a respective pair of backside dielectric isolation walls of the backside dielectric isolation walls;
one of the dielectric support pillar structures comprises a pair of vertically-extending lateral indentations; and
each of the vertically-extending lateral indentations is filled with a respective end portion of a respective one of the backside dielectric isolation walls.
17 . The three-dimensional memory device of claim 16 , wherein:
the end walls of the pair of vertically-extending lateral indentations are not parallel to each other, and are not perpendicular to each other; and
each surface of the pair of vertically-extending lateral indentations contacts a respective sidewall surface segment of the pair of backside dielectric isolation walls.
18 . The three-dimensional memory device of claim 1 , wherein:
a first subset of the backside dielectric isolation walls comprises a respective pair of first lengthwise sidewalls that are parallel to the first horizontal direction; and
a second subset of the backside dielectric isolation walls comprises a respective pair of second lengthwise sidewalls that are not parallel to, and are not perpendicular to, the first horizontal direction.
19 . A three-dimensional memory device, comprising:
alternating stacks of insulating layers and electrically conductive layers, wherein the alternating stacks are laterally spaced apart from each other by backside isolation assemblies that generally laterally extend along a first horizontal direction through entire heights of the alternating stacks with lateral undulations along a second horizontal direction that is perpendicular to the first horizontal direction, and wherein each of the alternating stacks has a modulation in width along the second horizontal direction as a function of a position along the first horizontal direction; and
memory stack structures that vertically extend through a respective one of the alternating stacks, and wherein each of the memory stack structures comprises a respective vertical semiconductor channel and a respective vertical stack of memory elements,
wherein:
each of the backside isolation assemblies comprises a respective laterally alternating sequence of backside dielectric isolation walls and dielectric support pillar structures such that a subset of the dielectric support pillar structures is in direct contact with a respective pair of backside dielectric isolation walls of the backside dielectric isolation walls;
wherein at least one of the dielectric support pillar structures has a respective pair of lateral indentations that is filled by end portions of a respective pair of backside dielectric isolation walls of the backside dielectric isolation walls;
the subset of the dielectric support pillar structures have circular, elliptical or oval horizontal cross-sectional shapes with a pair of vertically-extending lateral indentations; and
an additional subset of the dielectric support pillar structures have circular, elliptical or oval horizontal cross-sectional shapes and do not contact the backside dielectric isolation walls.