IP Library Granted Patent US 12,408,345
Granted Patent B2
US 12,408,345 · App. 18/524,552 · Granted Sep 2, 2025

Three-dimensional memory device with backside support pillar structures and methods of forming the same

Inventors: Shunsuke Takuma (Yokkaichi, JP); Yuji Totoki (Yokkaichi, JP); Seiji Shimabukuro (Yokkaichi, JP); Tatsuya Hinoue (Yokkaichi, JP); Kengo Kajiwara (Yokkaichi, JP); Akihiro Tobioka (Yokkaichi, JP)
Assignee: Sandisk Technologies, Inc.
H10B43/50H01L23/5226H01L23/562H10B41/27H10B41/50H10B43/27
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Quick Facts
Patent No.
US 12,408,345
App. No.
18/524,552
Granted
Sep 2, 2025
Kind
B2
Abstract

At least one vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate. Rows of backside support pillar structures are formed through the at least one vertically alternating sequence. Memory stack structures are formed through the at least one vertically alternating sequence. A two-dimensional array of discrete backside trenches is formed through the at least one vertically alternating sequence. Contiguous combinations of a subset of the backside trenches and a subset of the backside support pillar structures divide the at least one vertically alternating sequence into alternating stacks of insulating layers and sacrificial material layers. The sacrificial material layers are replaced with electrically conductive layers while the backside support pillar structures provide structural support to the insulating layers.

Claims (42)

1. A method of forming a semiconductor structure, comprising:

forming at least one vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers over a substrate;

forming rows of backside support pillar structures through the at least one vertically alternating sequence;

forming memory stack structures through the at least one vertically alternating sequence, wherein each of the memory stack structures comprises a respective vertical semiconductor channel and a respective vertical stack of memory elements;

forming a two-dimensional array of discrete backside trenches through the at least one vertically alternating sequence such that contiguous combinations of the discrete backside trenches and the backside support pillar structures are formed, wherein the contiguous combinations divide the at least one vertically alternating sequence into alternating stacks of insulating layers and sacrificial material layers, and wherein each of the insulating layers comprises a patterned portion of a respective one of the continuous insulating layers and each of the sacrificial material layers comprises a patterned portion of a respective one of the continuous sacrificial material layers; and

replacing the sacrificial material layers with electrically conductive layers by providing an etchant that etches the sacrificial material layers into the backside trenches and by providing a reactant that deposits the electrically conductive layers into the backside trenches while the backside support pillar structures provide structural support to the insulating layers,

wherein each of the contiguous combinations comprises a respective discrete backside trench and a respective set of two backside support pillar structures each having a respective set of at least one sidewall surface segment that is physically exposed to the respective discrete backside trench upon formation of the discrete backside trenches and prior to etching the sacrificial material layers.

2. The method of claim 1 , wherein the two-dimensional array of discrete backside trenches is formed by anisotropically etching portions of the at least one vertically alternating sequence and peripheral portions of the backside support pillar structures, wherein sidewalls of the backside support pillar structures are physically exposed to the backside trenches.

3. The method of claim 1 , wherein:

each row of the backside support pillar structures comprises a subset of the backside support pillar structures that are arranged along a first horizontal direction; and

the two-dimensional array of discrete backside trenches comprise rows of discrete backside trenches that are arranged along the first horizontal direction.

4. The method of claim 3 , wherein:

each of the discrete backside trenches comprises a respective pair of straight sidewalls that laterally extend along the first horizontal direction; and

each contiguous combination of a respective subset of the backside trenches and a respective subset of the backside support pillar structures laterally extends along the first horizontal direction.

5. The method of claim 1 , further comprising forming arrays of support pillar structures between the rows of backside support pillar structures and through the at least one vertically alternating sequence concurrently with formation of the backside support pillar structures.

6. The method of claim 1 , further comprising forming a contact-level dielectric layer over the at least one vertically alternating sequence and over the backside support pillar structures, wherein the two-dimensional periodic array of discrete backside trenches is formed through the contact-level dielectric layer and through the at least one vertically alternating sequence.

7. The method of claim 6 , further comprising forming backside dielectric isolation walls in the backside trenches by depositing a dielectric fill material in the backside trenches, wherein top surfaces of the backside dielectric isolation walls are formed within a horizontal plane including a top surface of the contact-level dielectric layer.

8. The method of claim 1 , wherein, for each contiguous combination, the respective set of at least one sidewall surface segment comprises a plurality of sidewall surface segments facing different horizontal directions that are not parallel or perpendicular to each other.

9. The method of claim 1 , wherein:

each continuous combination laterally extends along a first horizontal direction; and

for each contiguous combination, the respective set of at least one sidewall surface segment comprises a respective first sidewall surface segment that is parallel to the first horizontal direction.

10. The method of claim 9 , wherein, for each contiguous combination, the respective set of at least one sidewall surface segment comprises a respective second surface segment that is perpendicular to the first horizontal direction.

11. The method of claim 9 , wherein, for each contiguous combination, the respective set of at least one sidewall surface segment comprises two second surface segments of a backside support pillar structure within the respective set of two backside support pillar structures, the two second surface segments being perpendicular to the first horizontal direction.

12. The method of claim 1 , wherein sidewalls of the discrete backside trenches comprise surface segments of the backside support pillar structures.

13. The method of claim 1 , wherein one of the backside support pillar structures is patterned during formation of the discrete backside trenches such that sidewalls of said one of the backside support pillar structures comprise first sidewalls that are physically exposed to a first one of the discrete backside trenches and second sidewalls that are physically exposed to a second one of the discrete backside trenches.

14. The method of claim 13 , wherein a lateral spacing between the first one of the discrete backside trenches and the second one of the discrete backside trenches is less than a maximum lateral dimension of said one of the backside support pillar structures after formation of the discrete backside trenches along a separation direction between the first one of the discrete backside trenches and the second one of the discrete backside trenches.

15. The method of claim 13 , wherein a lateral dimension of said one of the backside support pillar structures along a horizontal direction that is perpendicular to a lateral separation direction between the first one of the discrete backside trenches and the second one of the discrete backside trenches is greater than a width of the first one of the discrete backside trenches along a horizontal direction that is perpendicular to the lateral separation direction between the first one of the discrete backside trenches and the second one of the discrete backside trenches.

16. The method of claim 1 , wherein sidewalls of one of the discrete backside trenches comprise:

first sidewall segments that are physically exposed surface segments a first backside support pillar structure of the backside support pillar structures; and

second sidewall segments that are physically exposed surface segments a second backside support pillar structure of the backside support pillar structures.

17. The method of claim 16 , wherein:

the discrete backside trenches laterally extend along a first horizontal direction; and

the physically exposed surface segments of the first backside support pillar structure comprise a sidewall surface segment that is parallel to the first horizontal direction and another sidewall surface segment that is perpendicular to the first horizontal direction.

18. The method of claim 16 , wherein:

the discrete backside trenches laterally extend along a first horizontal direction; and

the first backside support pillar structure and the second backside support pillar structure are laterally spaced from each other along the first horizontal direction.

19. The method of claim 18 , wherein the sidewalls of said one of the discrete backside trenches comprise:

third sidewall segments that are physically exposed surface segments a third backside support pillar structure of the backside support pillar structures; and

fourth sidewall segments that are physically exposed surface segments a fourth backside support pillar structure of the backside support pillar structures.

20. The method of claim 19 , wherein:

the third backside support pillar structure is laterally spaced from the first backside support pillar structure along a second horizontal direction that is perpendicular to the first horizontal direction; and

the fourth backside support pillar structure is laterally spaced from the second backside support pillar structure along the second horizontal direction.

Assignments (4)
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 31, 2024
From: SANDISK TECHNOLOGIES LLC
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 069796/0423 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 2, 2024
From: TAKUMA, SHUNSUKE; TOTOKI, YUJI; SHIMABUKURO, SEIJI; HINOUE, TATSUYA; KAJIWARA, KENGO; TOBIOKA, AKIHIRO
To: SANDISK TECHNOLOGIES LLC
Reel/Frame 065991/0847 →
Continuity (2)
Division 17146866 · Jan 12, 2021
Related Publication 20240099014A1 · Mar 21, 2024
References Cited (38)
US 5915167A · Leed · 1999 [cited by applicant]
US 9543318B1 · Lu et al. · 2017 [cited by applicant]
US 9679906B2 · Lu et al. · 2017 [cited by applicant]
US 10115681B1 · Ariyoshi · 2018 [cited by applicant]
US 11081443B1 · Mizutani et al. · 2021 [cited by applicant]
US 11114459B2 · Iwai et al. · 2021 [cited by applicant]
US 11133252B2 · Ito et al. · 2021 [cited by applicant]
US 11139237B2 · Shao et al. · 2021 [cited by applicant]
US 11342245B2 · Cui et al. · 2022 [cited by applicant]
US 11349066B2 · Kalitsov et al. · 2022 [cited by applicant]
US 11355506B2 · Tokita et al. · 2022 [cited by applicant]
US 11380707B2 · Matsuno et al. · 2022 [cited by applicant]
US 11398497B2 · Kajiwara et al. · 2022 [cited by applicant]
US 11411170B2 · Kalitsov et al. · 2022 [cited by applicant]
US 11417379B2 · Kalitsov et al. · 2022 [cited by applicant]
US 20170179154A1 · Furihata · 2017 [cited by examiner]
US 20170358593A1 · Yu et al. · 2017 [cited by applicant]
US 20190259881A1 · Kim et al. · 2019 [cited by applicant]
US 20190371809A1 · Yu et al. · 2019 [cited by applicant]
US 20200235120A1 · Kai et al. · 2020 [cited by applicant]
US 20200251485A1 · Kakazu et al. · 2020 [cited by applicant]
US 20210057336A1 · Shao et al. · 2021 [cited by applicant]
US 20210134827A1 · Iwai et al. · 2021 [cited by applicant]
US 20210242128A1 · Ito et al. · 2021 [cited by applicant]
US 20210249432A1 · Eom · 2021 [cited by applicant]
US 20210358936A1 · Takuma et al. · 2021 [cited by applicant]
US 20210358937A1 · Yamaguchi et al. · 2021 [cited by applicant]
US 20210358941A1 · Kajiwara et al. · 2021 [cited by applicant]
US 20210366808A1 · Cui et al. · 2021 [cited by applicant]
US 20210366920A1 · Tokita et al. · 2021 [cited by applicant]
US 20210366924A1 · Tokita et al. · 2021 [cited by applicant]
US 20220181348A1 · Matsuno et al. · 2022 [cited by applicant]
US 20220223614A1 · Takuma et al. · 2022 [cited by applicant]
Endoh et al., “Novel Ultra High-Density Memory with a Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell,” IEDM Proc. (2001) 33-36. [cited by applicant]
Notification of Transmittal of the International Search Report and the Written Opinion of the International Searching Authority for International Patent Application No. PCT/US2021/035784, mailed on Nov. 11, 2021, 11 pag… [cited by applicant]
USPTO Office Communication, Non-Final Office Action for U.S. Appl. No. 18/442,792, mailed Nov. 21, 2024, 15 pages. [cited by applicant]
USPTO Office Communication, Final Office Action for U.S. Appl. No. 18/442,792, mailed on Feb. 24, 2025, 11 pages. [cited by applicant]
USPTO Office Communication, Non-Final Office Action for U.S. Appl. No. 18/524,552, mailed on Feb. 26, 2025, 13 pages. [cited by applicant]